Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / b3e9dc6705fff61d56c6833d21927a9122d6ab0f / . / arch / sandbox / dts / test.dts
blob: 87d8e5bcc98b4ac8e4cd774d60250e39f4c6b04c [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]7 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]8
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]12 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]13 eth5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]14 gpio1 = &gpio_a;
15 gpio2 = &gpio_b;
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]16 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -0600[diff] [blame]17 mmc0 = "/mmc0";
18 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]19 pci0 = &pci0;
20 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]21 pci2 = &pci2;
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]22 remoteproc1 = &rproc_1;
23 remoteproc2 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]24 rtc0 = &rtc_0;
25 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]26 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +0200[diff] [blame]27 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]28 testbus3 = "/some-bus";
29 testfdt0 = "/some-bus/c-test@0";
30 testfdt1 = "/some-bus/c-test@1";
31 testfdt3 = "/b-test";
32 testfdt5 = "/some-bus/c-test@5";
33 testfdt8 = "/a-test";
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +0200[diff] [blame]34 fdt-dummy0 = "/translation-test@8000/dev@0,0";
35 fdt-dummy1 = "/translation-test@8000/dev@1,100";
36 fdt-dummy2 = "/translation-test@8000/dev@2,200";
37 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]38 usb0 = &usb_0;
39 usb1 = &usb_1;
40 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]41 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +0200[diff] [blame]42 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]43 };
44
Simon Glassed96cde2018-12-10 10:37:33 -0700[diff] [blame]45 audio: audio-codec {
46 compatible = "sandbox,audio-codec";
47 #sound-dai-cells = <1>;
48 };
49
Simon Glassc953aaf2018-12-10 10:37:34 -0700[diff] [blame]50 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600[diff] [blame]51 reg = <0 0>;
52 compatible = "google,cros-ec-sandbox";
53
54 /*
55 * This describes the flash memory within the EC. Note
56 * that the STM32L flash erases to 0, not 0xff.
57 */
58 flash {
59 image-pos = <0x08000000>;
60 size = <0x20000>;
61 erase-value = <0>;
62
63 /* Information for sandbox */
64 ro {
65 image-pos = <0>;
66 size = <0xf000>;
67 };
68 wp-ro {
69 image-pos = <0xf000>;
70 size = <0x1000>;
71 };
72 rw {
73 image-pos = <0x10000>;
74 size = <0x10000>;
75 };
76 };
77 };
78
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]79 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]80 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]81 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]82 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]83 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]84 u-boot,dm-pre-reloc;
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]85 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
86 <0>, <&gpio_a 12>;
87 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
88 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
89 <&gpio_b 9 0xc 3 2 1>;
Simon Glass6df01f92018-12-10 10:37:37 -0700[diff] [blame]90 int-value = <1234>;
91 uint-value = <(-1234)>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]92 };
93
94 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]95 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]96 compatible = "not,compatible";
97 };
98
99 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]100 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]101 };
102
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]103 backlight: backlight {
104 compatible = "pwm-backlight";
105 enable-gpios = <&gpio_a 1>;
106 power-supply = <&ldo_1>;
107 pwms = <&pwm 0 1000>;
108 default-brightness-level = <5>;
109 brightness-levels = <0 16 32 64 128 170 202 234 255>;
110 };
111
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200[diff] [blame]112 bind-test {
113 bind-test-child1 {
114 compatible = "sandbox,phy";
115 #phy-cells = <1>;
116 };
117
118 bind-test-child2 {
119 compatible = "simple-bus";
120 };
121 };
122
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]123 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]124 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]125 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]126 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]127 ping-add = <3>;
128 };
129
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200[diff] [blame]130 phy_provider0: gen_phy@0 {
131 compatible = "sandbox,phy";
132 #phy-cells = <1>;
133 };
134
135 phy_provider1: gen_phy@1 {
136 compatible = "sandbox,phy";
137 #phy-cells = <0>;
138 broken;
139 };
140
141 gen_phy_user: gen_phy_user {
142 compatible = "simple-bus";
143 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
144 phy-names = "phy1", "phy2", "phy3";
145 };
146
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]147 some-bus {
148 #address-cells = <1>;
149 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]150 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]151 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]152 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]153 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]154 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]155 compatible = "denx,u-boot-fdt-test";
156 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]157 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]158 ping-add = <5>;
159 };
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]160 c-test@0 {
161 compatible = "denx,u-boot-fdt-test";
162 reg = <0>;
163 ping-expect = <6>;
164 ping-add = <6>;
165 };
166 c-test@1 {
167 compatible = "denx,u-boot-fdt-test";
168 reg = <1>;
169 ping-expect = <7>;
170 ping-add = <7>;
171 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]172 };
173
174 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]175 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600[diff] [blame]176 ping-expect = <6>;
177 ping-add = <6>;
178 compatible = "google,another-fdt-test";
179 };
180
181 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]182 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]183 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]184 ping-add = <6>;
185 compatible = "google,another-fdt-test";
186 };
187
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]188 f-test {
189 compatible = "denx,u-boot-fdt-test";
190 };
191
192 g-test {
193 compatible = "denx,u-boot-fdt-test";
194 };
195
Bin Mengd9d24782018-10-10 22:07:01 -0700[diff] [blame]196 h-test {
197 compatible = "denx,u-boot-fdt-test1";
198 };
199
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200[diff] [blame]200 clocks {
201 clk_fixed: clk-fixed {
202 compatible = "fixed-clock";
203 #clock-cells = <0>;
204 clock-frequency = <1234>;
205 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000[diff] [blame]206
207 clk_fixed_factor: clk-fixed-factor {
208 compatible = "fixed-factor-clock";
209 #clock-cells = <0>;
210 clock-div = <3>;
211 clock-mult = <2>;
212 clocks = <&clk_fixed>;
213 };
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]214 };
215
216 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]217 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]218 #clock-cells = <1>;
219 };
220
221 clk-test {
222 compatible = "sandbox,clk-test";
223 clocks = <&clk_fixed>,
224 <&clk_sandbox 1>,
225 <&clk_sandbox 0>;
226 clock-names = "fixed", "i2c", "spi";
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]227 };
228
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]229 eth@10002000 {
230 compatible = "sandbox,eth";
231 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]232 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]233 };
234
235 eth_5: eth@10003000 {
236 compatible = "sandbox,eth";
237 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]238 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]239 };
240
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]241 eth_3: sbe5 {
242 compatible = "sandbox,eth";
243 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]244 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]245 };
246
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]247 eth@10004000 {
248 compatible = "sandbox,eth";
249 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]250 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]251 };
252
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700[diff] [blame]253 firmware {
254 sandbox_firmware: sandbox-firmware {
255 compatible = "sandbox,firmware";
256 };
257 };
258
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]259 gpio_a: base-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]260 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]261 gpio-controller;
262 #gpio-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]263 gpio-bank-name = "a";
Simon Glass9e7ab232018-02-03 10:36:59 -0700[diff] [blame]264 sandbox,gpio-count = <20>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]265 };
266
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]267 gpio_b: extra-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]268 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]269 gpio-controller;
270 #gpio-cells = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]271 gpio-bank-name = "b";
Simon Glass9e7ab232018-02-03 10:36:59 -0700[diff] [blame]272 sandbox,gpio-count = <10>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]273 };
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]274
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]275 i2c@0 {
276 #address-cells = <1>;
277 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]278 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]279 compatible = "sandbox,i2c";
280 clock-frequency = <100000>;
281 eeprom@2c {
282 reg = <0x2c>;
283 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]284 sandbox,emul = <&emul_eeprom>;
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]285 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]286
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]287 rtc_0: rtc@43 {
288 reg = <0x43>;
289 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]290 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]291 };
292
293 rtc_1: rtc@61 {
294 reg = <0x61>;
295 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]296 sandbox,emul = <&emul1>;
297 };
298
299 i2c_emul: emul {
300 reg = <0xff>;
301 compatible = "sandbox,i2c-emul-parent";
302 emul_eeprom: emul-eeprom {
303 compatible = "sandbox,i2c-eeprom";
304 sandbox,filename = "i2c.bin";
305 sandbox,size = <256>;
306 };
307 emul0: emul0 {
308 compatible = "sandbox,i2c-rtc";
309 };
310 emul1: emull {
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]311 compatible = "sandbox,i2c-rtc";
312 };
313 };
314
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]315 sandbox_pmic: sandbox_pmic {
316 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]317 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]318 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200[diff] [blame]319
320 mc34708: pmic@41 {
321 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]322 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200[diff] [blame]323 };
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]324 };
325
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100[diff] [blame]326 bootcount@0 {
327 compatible = "u-boot,bootcount-rtc";
328 rtc = <&rtc_1>;
329 offset = <0x13>;
330 };
331
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100[diff] [blame]332 adc@0 {
333 compatible = "sandbox,adc";
334 vdd-supply = <&buck2>;
335 vss-microvolts = <0>;
336 };
337
Simon Glass90b6fef2016-01-18 19:52:26 -0700[diff] [blame]338 lcd {
339 u-boot,dm-pre-reloc;
340 compatible = "sandbox,lcd-sdl";
341 xres = <1366>;
342 yres = <768>;
343 };
344
Simon Glassd783eb32015-07-06 12:54:34 -0600[diff] [blame]345 leds {
346 compatible = "gpio-leds";
347
348 iracibble {
349 gpios = <&gpio_a 1 0>;
350 label = "sandbox:red";
351 };
352
353 martinet {
354 gpios = <&gpio_a 2 0>;
355 label = "sandbox:green";
356 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200[diff] [blame]357
358 default_on {
359 gpios = <&gpio_a 5 0>;
360 label = "sandbox:default_on";
361 default-state = "on";
362 };
363
364 default_off {
365 gpios = <&gpio_a 6 0>;
366 label = "sandbox:default_off";
367 default-state = "off";
368 };
Simon Glassd783eb32015-07-06 12:54:34 -0600[diff] [blame]369 };
370
Stephen Warren62f2c902016-05-16 17:41:37 -0600[diff] [blame]371 mbox: mbox {
372 compatible = "sandbox,mbox";
373 #mbox-cells = <1>;
374 };
375
376 mbox-test {
377 compatible = "sandbox,mbox-test";
378 mboxes = <&mbox 100>, <&mbox 1>;
379 mbox-names = "other", "test";
380 };
381
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]382 cpu-test1 {
383 compatible = "sandbox,cpu_sandbox";
Bin Mengda3e72f2018-10-14 01:07:20 -0700[diff] [blame]384 u-boot,dm-pre-reloc;
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]385 };
386
387 cpu-test2 {
388 compatible = "sandbox,cpu_sandbox";
Bin Mengda3e72f2018-10-14 01:07:20 -0700[diff] [blame]389 u-boot,dm-pre-reloc;
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]390 };
391
392 cpu-test3 {
393 compatible = "sandbox,cpu_sandbox";
Bin Mengda3e72f2018-10-14 01:07:20 -0700[diff] [blame]394 u-boot,dm-pre-reloc;
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]395 };
396
Simon Glassc953aaf2018-12-10 10:37:34 -0700[diff] [blame]397 i2s: i2s {
398 compatible = "sandbox,i2s";
399 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700[diff] [blame]400 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700[diff] [blame]401 };
402
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200[diff] [blame]403 misc-test {
404 compatible = "sandbox,misc_sandbox";
405 };
406
Simon Glasse4fef742017-04-23 20:02:07 -0600[diff] [blame]407 mmc2 {
408 compatible = "sandbox,mmc";
409 };
410
411 mmc1 {
412 compatible = "sandbox,mmc";
413 };
414
415 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600[diff] [blame]416 compatible = "sandbox,mmc";
417 };
418
Simon Glass53a68b32019-02-16 20:24:50 -0700[diff] [blame]419 pch {
420 compatible = "sandbox,pch";
421 };
422
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]423 pci0: pci-controller0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]424 compatible = "sandbox,pci";
425 device_type = "pci";
426 #address-cells = <3>;
427 #size-cells = <2>;
428 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
429 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700[diff] [blame]430 pci@0,0 {
431 compatible = "pci-generic";
432 reg = <0x0000 0 0 0 0>;
433 emul@0,0 {
434 compatible = "sandbox,swap-case";
435 };
436 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]437 pci@1f,0 {
438 compatible = "pci-generic";
439 reg = <0xf800 0 0 0 0>;
440 emul@1f,0 {
441 compatible = "sandbox,swap-case";
442 };
443 };
444 };
445
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]446 pci1: pci-controller1 {
447 compatible = "sandbox,pci";
448 device_type = "pci";
449 #address-cells = <3>;
450 #size-cells = <2>;
451 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
452 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700[diff] [blame]453 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200[diff] [blame]454 0x0c 0x00 0x1234 0x5678
455 0x10 0x00 0x1234 0x5678>;
456 pci@10,0 {
457 reg = <0x8000 0 0 0 0>;
458 };
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]459 };
460
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]461 pci2: pci-controller2 {
462 compatible = "sandbox,pci";
463 device_type = "pci";
464 #address-cells = <3>;
465 #size-cells = <2>;
466 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
467 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
468 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
469 pci@1f,0 {
470 compatible = "pci-generic";
471 reg = <0xf800 0 0 0 0>;
472 emul@1f,0 {
473 compatible = "sandbox,swap-case";
474 };
475 };
476 };
477
Simon Glass9c433fe2017-04-23 20:10:44 -0600[diff] [blame]478 probing {
479 compatible = "simple-bus";
480 test1 {
481 compatible = "denx,u-boot-probe-test";
482 };
483
484 test2 {
485 compatible = "denx,u-boot-probe-test";
486 };
487
488 test3 {
489 compatible = "denx,u-boot-probe-test";
490 };
491
492 test4 {
493 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100[diff] [blame]494 first-syscon = <&syscon0>;
495 second-sys-ctrl = <&another_system_controller>;
Simon Glass9c433fe2017-04-23 20:10:44 -0600[diff] [blame]496 };
497 };
498
Stephen Warren92c67fa2016-07-13 13:45:31 -0600[diff] [blame]499 pwrdom: power-domain {
500 compatible = "sandbox,power-domain";
501 #power-domain-cells = <1>;
502 };
503
504 power-domain-test {
505 compatible = "sandbox,power-domain-test";
506 power-domains = <&pwrdom 2>;
507 };
508
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]509 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]510 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]511 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]512 };
513
514 pwm2 {
515 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]516 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]517 };
518
Simon Glass3d355e62015-07-06 12:54:31 -0600[diff] [blame]519 ram {
520 compatible = "sandbox,ram";
521 };
522
Simon Glassd860f222015-07-06 12:54:29 -0600[diff] [blame]523 reset@0 {
524 compatible = "sandbox,warm-reset";
525 };
526
527 reset@1 {
528 compatible = "sandbox,reset";
529 };
530
Stephen Warren6488e642016-06-17 09:43:59 -0600[diff] [blame]531 resetc: reset-ctl {
532 compatible = "sandbox,reset-ctl";
533 #reset-cells = <1>;
534 };
535
536 reset-ctl-test {
537 compatible = "sandbox,reset-ctl-test";
538 resets = <&resetc 100>, <&resetc 2>;
539 reset-names = "other", "test";
540 };
541
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]542 rproc_1: rproc@1 {
543 compatible = "sandbox,test-processor";
544 remoteproc-name = "remoteproc-test-dev1";
545 };
546
547 rproc_2: rproc@2 {
548 compatible = "sandbox,test-processor";
549 internal-memory-mapped;
550 remoteproc-name = "remoteproc-test-dev2";
551 };
552
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]553 panel {
554 compatible = "simple-panel";
555 backlight = <&backlight 0 100>;
556 };
557
Ramon Fried26ed32e2018-07-02 02:57:59 +0300[diff] [blame]558 smem@0 {
559 compatible = "sandbox,smem";
560 };
561
Simon Glass76072ac2018-12-10 10:37:36 -0700[diff] [blame]562 sound {
563 compatible = "sandbox,sound";
564 cpu {
565 sound-dai = <&i2s 0>;
566 };
567
568 codec {
569 sound-dai = <&audio 0>;
570 };
571 };
572
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]573 spi@0 {
574 #address-cells = <1>;
575 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]576 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]577 compatible = "sandbox,spi";
578 cs-gpios = <0>, <&gpio_a 0>;
579 spi.bin@0 {
580 reg = <0>;
581 compatible = "spansion,m25p16", "spi-flash";
582 spi-max-frequency = <40000000>;
583 sandbox,filename = "spi.bin";
584 };
585 };
586
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100[diff] [blame]587 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]588 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +0200[diff] [blame]589 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]590 };
591
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100[diff] [blame]592 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]593 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]594 reg = <0x20 5
595 0x28 6
596 0x30 7
597 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]598 };
599
Masahiro Yamada42ab1072018-04-23 13:26:53 +0900[diff] [blame]600 syscon@2 {
601 compatible = "simple-mfd", "syscon";
602 reg = <0x40 5
603 0x48 6
604 0x50 7
605 0x58 8>;
606 };
607
Thomas Chou6f2cfbf2015-12-11 16:27:34 +0800[diff] [blame]608 timer {
609 compatible = "sandbox,timer";
610 clock-frequency = <1000000>;
611 };
612
Miquel Raynal80938c12018-05-15 11:57:27 +0200[diff] [blame]613 tpm2 {
614 compatible = "sandbox,tpm2";
615 };
616
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]617 uart0: serial {
618 compatible = "sandbox,serial";
619 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -0500[diff] [blame]620 };
621
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]622 usb_0: usb@0 {
623 compatible = "sandbox,usb";
624 status = "disabled";
625 hub {
626 compatible = "sandbox,usb-hub";
627 #address-cells = <1>;
628 #size-cells = <0>;
629 flash-stick {
630 reg = <0>;
631 compatible = "sandbox,usb-flash";
632 };
633 };
634 };
635
636 usb_1: usb@1 {
637 compatible = "sandbox,usb";
638 hub {
639 compatible = "usb-hub";
640 usb,device-class = <9>;
641 hub-emul {
642 compatible = "sandbox,usb-hub";
643 #address-cells = <1>;
644 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -0700[diff] [blame]645 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]646 reg = <0>;
647 compatible = "sandbox,usb-flash";
648 sandbox,filepath = "testflash.bin";
649 };
650
Simon Glass4700fe52015-11-08 23:48:01 -0700[diff] [blame]651 flash-stick@1 {
652 reg = <1>;
653 compatible = "sandbox,usb-flash";
654 sandbox,filepath = "testflash1.bin";
655 };
656
657 flash-stick@2 {
658 reg = <2>;
659 compatible = "sandbox,usb-flash";
660 sandbox,filepath = "testflash2.bin";
661 };
662
Simon Glassc0ccc722015-11-08 23:48:08 -0700[diff] [blame]663 keyb@3 {
664 reg = <3>;
665 compatible = "sandbox,usb-keyb";
666 };
667
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]668 };
669 };
670 };
671
672 usb_2: usb@2 {
673 compatible = "sandbox,usb";
674 status = "disabled";
675 };
676
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200[diff] [blame]677 spmi: spmi@0 {
678 compatible = "sandbox,spmi";
679 #address-cells = <0x1>;
680 #size-cells = <0x1>;
681 pm8916@0 {
682 compatible = "qcom,spmi-pmic";
683 reg = <0x0 0x1>;
684 #address-cells = <0x1>;
685 #size-cells = <0x1>;
686
687 spmi_gpios: gpios@c000 {
688 compatible = "qcom,pm8916-gpio";
689 reg = <0xc000 0x400>;
690 gpio-controller;
691 gpio-count = <4>;
692 #gpio-cells = <2>;
693 gpio-bank-name="spmi";
694 };
695 };
696 };
maxims@google.comdaea6d42017-04-17 12:00:21 -0700[diff] [blame]697
698 wdt0: wdt@0 {
699 compatible = "sandbox,wdt";
700 };
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]701
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]702 axi: axi@0 {
703 compatible = "sandbox,axi";
704 #address-cells = <0x1>;
705 #size-cells = <0x1>;
706 store@0 {
707 compatible = "sandbox,sandbox_store";
708 reg = <0x0 0x400>;
709 };
710 };
711
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]712 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -0700[diff] [blame]713 #address-cells = <1>;
714 #size-cells = <1>;
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]715 chosen-test {
716 compatible = "denx,u-boot-fdt-test";
717 reg = <9 1>;
718 };
719 };
Mario Six35616ef2018-03-12 14:53:33 +0100[diff] [blame]720
721 translation-test@8000 {
722 compatible = "simple-bus";
723 reg = <0x8000 0x4000>;
724
725 #address-cells = <0x2>;
726 #size-cells = <0x1>;
727
728 ranges = <0 0x0 0x8000 0x1000
729 1 0x100 0x9000 0x1000
730 2 0x200 0xA000 0x1000
731 3 0x300 0xB000 0x1000
732 >;
733
734 dev@0,0 {
735 compatible = "denx,u-boot-fdt-dummy";
736 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +0100[diff] [blame]737 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +0100[diff] [blame]738 };
739
740 dev@1,100 {
741 compatible = "denx,u-boot-fdt-dummy";
742 reg = <1 0x100 0x1000>;
743
744 };
745
746 dev@2,200 {
747 compatible = "denx,u-boot-fdt-dummy";
748 reg = <2 0x200 0x1000>;
749 };
750
751
752 noxlatebus@3,300 {
753 compatible = "simple-bus";
754 reg = <3 0x300 0x1000>;
755
756 #address-cells = <0x1>;
757 #size-cells = <0x0>;
758
759 dev@42 {
760 compatible = "denx,u-boot-fdt-dummy";
761 reg = <0x42>;
762 };
763 };
764 };
Mario Six02ad6fb2018-09-27 09:19:31 +0200[diff] [blame]765
766 osd {
767 compatible = "sandbox,sandbox_osd";
768 };
Tom Rinib93eea72018-09-30 18:16:51 -0400[diff] [blame]769
Mario Sixab664ff2018-07-31 11:44:13 +0200[diff] [blame]770 board {
771 compatible = "sandbox,board_sandbox";
772 };
Jens Wiklander86afaa62018-09-25 16:40:16 +0200[diff] [blame]773
774 sandbox_tee {
775 compatible = "sandbox,tee";
776 };
Bin Meng1bb290d2018-10-15 02:21:26 -0700[diff] [blame]777
778 sandbox_virtio1 {
779 compatible = "sandbox,virtio1";
780 };
781
782 sandbox_virtio2 {
783 compatible = "sandbox,virtio2";
784 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +0200[diff] [blame]785
786 pinctrl {
787 compatible = "sandbox,pinctrl";
788 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +0100[diff] [blame]789
790 hwspinlock@0 {
791 compatible = "sandbox,hwspinlock";
792 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]793
794 dma: dma {
795 compatible = "sandbox,dma";
796 #dma-cells = <1>;
797
798 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
799 dma-names = "m2m", "tx0", "rx0";
800 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]801};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]802
803#include "sandbox_pmic.dtsi"