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Stefano Babic7b07f092010-01-20 18:19:10 +01001/*
2 * (C) Copyright 2009
3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefano Babic7b07f092010-01-20 18:19:10 +01006 */
7
8#ifndef _IMXIMAGE_H_
9#define _IMXIMAGE_H_
10
Fabio Estevam7b9849f2014-09-01 09:56:23 -030011#define MAX_HW_CFG_SIZE_V2 220 /* Max number of registers imx can set for v2 */
Liu Hui-R643434aa360a2011-01-19 09:40:26 +000012#define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */
Stefano Babic7b07f092010-01-20 18:19:10 +010013#define APP_CODE_BARKER 0xB1
14#define DCD_BARKER 0xB17219E9
Stefano Babic7b07f092010-01-20 18:19:10 +010015
Marek Vasutd45fd732013-04-25 10:16:02 +000016/*
17 * NOTE: This file must be kept in sync with arch/arm/include/asm/\
18 * imx-common/imximage.cfg because tools/imximage.c can not
19 * cross-include headers from arch/arm/ and vice-versa.
20 */
Stefano Babic7b07f092010-01-20 18:19:10 +010021#define CMD_DATA_STR "DATA"
Stefano Babicdc39a3e2013-06-26 23:50:06 +020022
23/* Initial Vector Table Offset */
Dirk Behme14a98cd2012-02-22 22:50:19 +000024#define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
Stefano Babic7b07f092010-01-20 18:19:10 +010025#define FLASH_OFFSET_STANDARD 0x400
26#define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD
27#define FLASH_OFFSET_SD FLASH_OFFSET_STANDARD
28#define FLASH_OFFSET_SPI FLASH_OFFSET_STANDARD
29#define FLASH_OFFSET_ONENAND 0x100
Dirk Behmedfbf6ce2012-01-11 23:28:31 +000030#define FLASH_OFFSET_NOR 0x1000
31#define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD
Ye.Lif16cde02015-01-13 15:53:06 +080032#define FLASH_OFFSET_QSPI 0x1000
Stefano Babic7b07f092010-01-20 18:19:10 +010033
Stefano Babicdc39a3e2013-06-26 23:50:06 +020034/* Initial Load Region Size */
35#define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF
36#define FLASH_LOADSIZE_STANDARD 0x1000
37#define FLASH_LOADSIZE_NAND FLASH_LOADSIZE_STANDARD
38#define FLASH_LOADSIZE_SD FLASH_LOADSIZE_STANDARD
39#define FLASH_LOADSIZE_SPI FLASH_LOADSIZE_STANDARD
40#define FLASH_LOADSIZE_ONENAND 0x400
41#define FLASH_LOADSIZE_NOR 0x0 /* entire image */
42#define FLASH_LOADSIZE_SATA FLASH_LOADSIZE_STANDARD
Ye.Lif16cde02015-01-13 15:53:06 +080043#define FLASH_LOADSIZE_QSPI 0x0 /* entire image */
Stefano Babicdc39a3e2013-06-26 23:50:06 +020044
Liu Hui-R643434aa360a2011-01-19 09:40:26 +000045#define IVT_HEADER_TAG 0xD1
46#define IVT_VERSION 0x40
47#define DCD_HEADER_TAG 0xD2
48#define DCD_COMMAND_TAG 0xCC
49#define DCD_VERSION 0x40
50#define DCD_COMMAND_PARAM 0x4
51
Stefano Babic7b07f092010-01-20 18:19:10 +010052enum imximage_cmd {
53 CMD_INVALID,
Liu Hui-R643434aa360a2011-01-19 09:40:26 +000054 CMD_IMAGE_VERSION,
Stefano Babic7b07f092010-01-20 18:19:10 +010055 CMD_BOOT_FROM,
Marek Vasutd45fd732013-04-25 10:16:02 +000056 CMD_BOOT_OFFSET,
Stefano Babic4aa97492013-06-27 11:42:38 +020057 CMD_DATA,
58 CMD_CSF,
Stefano Babic7b07f092010-01-20 18:19:10 +010059};
60
61enum imximage_fld_types {
62 CFG_INVALID = -1,
63 CFG_COMMAND,
64 CFG_REG_SIZE,
65 CFG_REG_ADDRESS,
66 CFG_REG_VALUE
67};
68
Liu Hui-R643434aa360a2011-01-19 09:40:26 +000069enum imximage_version {
70 IMXIMAGE_VER_INVALID = -1,
71 IMXIMAGE_V1 = 1,
72 IMXIMAGE_V2
73};
Stefano Babic7b07f092010-01-20 18:19:10 +010074
75typedef struct {
76 uint32_t type; /* Type of pointer (byte, halfword, word, wait/read) */
77 uint32_t addr; /* Address to write to */
78 uint32_t value; /* Data to write */
79} dcd_type_addr_data_t;
80
81typedef struct {
82 uint32_t barker; /* Barker for sanity check */
83 uint32_t length; /* Device configuration length (without preamble) */
84} dcd_preamble_t;
85
86typedef struct {
87 dcd_preamble_t preamble;
Liu Hui-R643434aa360a2011-01-19 09:40:26 +000088 dcd_type_addr_data_t addr_data[MAX_HW_CFG_SIZE_V1];
89} dcd_v1_t;
Stefano Babic7b07f092010-01-20 18:19:10 +010090
91typedef struct {
92 uint32_t app_code_jump_vector;
93 uint32_t app_code_barker;
94 uint32_t app_code_csf;
95 uint32_t dcd_ptr_ptr;
Stefano Babic5cdde802010-02-05 15:16:02 +010096 uint32_t super_root_key;
Stefano Babic7b07f092010-01-20 18:19:10 +010097 uint32_t dcd_ptr;
98 uint32_t app_dest_ptr;
Liu Hui-R643434aa360a2011-01-19 09:40:26 +000099} flash_header_v1_t;
Stefano Babic7b07f092010-01-20 18:19:10 +0100100
101typedef struct {
102 uint32_t length; /* Length of data to be read from flash */
103} flash_cfg_parms_t;
104
Liu Hui-R643434aa360a2011-01-19 09:40:26 +0000105typedef struct {
106 flash_header_v1_t fhdr;
107 dcd_v1_t dcd_table;
Stefano Babic7b07f092010-01-20 18:19:10 +0100108 flash_cfg_parms_t ext_header;
Liu Hui-R643434aa360a2011-01-19 09:40:26 +0000109} imx_header_v1_t;
110
111typedef struct {
112 uint32_t addr;
113 uint32_t value;
114} dcd_addr_data_t;
115
116typedef struct {
117 uint8_t tag;
118 uint16_t length;
119 uint8_t version;
120} __attribute__((packed)) ivt_header_t;
121
122typedef struct {
123 uint8_t tag;
124 uint16_t length;
125 uint8_t param;
126} __attribute__((packed)) write_dcd_command_t;
127
128typedef struct {
129 ivt_header_t header;
130 write_dcd_command_t write_dcd_command;
131 dcd_addr_data_t addr_data[MAX_HW_CFG_SIZE_V2];
132} dcd_v2_t;
133
134typedef struct {
135 uint32_t start;
136 uint32_t size;
137 uint32_t plugin;
138} boot_data_t;
139
140typedef struct {
141 ivt_header_t header;
142 uint32_t entry;
143 uint32_t reserved1;
144 uint32_t dcd_ptr;
145 uint32_t boot_data_ptr;
146 uint32_t self;
147 uint32_t csf;
148 uint32_t reserved2;
149} flash_header_v2_t;
150
151typedef struct {
152 flash_header_v2_t fhdr;
153 boot_data_t boot_data;
154 dcd_v2_t dcd_table;
155} imx_header_v2_t;
156
Marek Vasut3d1acc62013-04-21 05:52:22 +0000157/* The header must be aligned to 4k on MX53 for NAND boot */
Liu Hui-R643434aa360a2011-01-19 09:40:26 +0000158struct imx_header {
159 union {
160 imx_header_v1_t hdr_v1;
161 imx_header_v2_t hdr_v2;
162 } header;
Stefano Babicdc39a3e2013-06-26 23:50:06 +0200163};
Stefano Babic7b07f092010-01-20 18:19:10 +0100164
Liu Hui-R643434aa360a2011-01-19 09:40:26 +0000165typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
166 char *name, int lineno,
167 int fld, uint32_t value,
168 uint32_t off);
169
170typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
171 uint32_t dcd_len,
172 char *name, int lineno);
173
Troy Kisky7bb92202012-10-03 15:47:08 +0000174typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
175 uint32_t entry_point, uint32_t flash_offset);
Stefano Babic7b07f092010-01-20 18:19:10 +0100176
177#endif /* _IMXIMAGE_H_ */