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git01.mediatek.com / filogic / uboot / b3daeaa5f0b75af5b52353fc83566c8686edd10f / . / include / linux / mtd / fsl_upm.h
blob: 9999993543baa94651309ea9edcf36c17a483a10 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Anton Vorontsov6ab97e92008-01-14 23:09:32 +0300[diff] [blame]2/*
3 * FSL UPM NAND driver
4 *
5 * Copyright (C) 2007 MontaVista Software, Inc.
6 * Anton Vorontsov <avorontsov@ru.mvista.com>
Anton Vorontsov6ab97e92008-01-14 23:09:32 +0300[diff] [blame]7 */
8
9#ifndef __LINUX_MTD_NAND_FSL_UPM
10#define __LINUX_MTD_NAND_FSL_UPM
11
Masahiro Yamada2b7a8732017-11-30 13:45:24 +0900[diff] [blame]12#include <linux/mtd/rawnand.h>
Anton Vorontsov6ab97e92008-01-14 23:09:32 +0300[diff] [blame]13
Wolfgang Grandegger64de8db2009-02-11 18:38:23 +0100[diff] [blame]14#define FSL_UPM_WAIT_RUN_PATTERN 0x1
15#define FSL_UPM_WAIT_WRITE_BYTE 0x2
16#define FSL_UPM_WAIT_WRITE_BUFFER 0x4
17
Anton Vorontsov6ab97e92008-01-14 23:09:32 +0300[diff] [blame]18struct fsl_upm {
Anton Vorontsov6ab97e92008-01-14 23:09:32 +0300[diff] [blame]19 void __iomem *mdr;
20 void __iomem *mxmr;
21 void __iomem *mar;
22 void __iomem *io_addr;
23};
24
25struct fsl_upm_nand {
26 struct fsl_upm upm;
27
28 int width;
29 int upm_cmd_offset;
30 int upm_addr_offset;
Wolfgang Grandeggerac205332009-02-11 18:38:22 +0100[diff] [blame]31 int upm_mar_chip_offset;
Wolfgang Grandegger64de8db2009-02-11 18:38:23 +0100[diff] [blame]32 int wait_flags;
Wolfgang Grandeggerf1540442009-02-11 18:38:21 +0100[diff] [blame]33 int (*dev_ready)(int chip_nr);
Anton Vorontsov6ab97e92008-01-14 23:09:32 +0300[diff] [blame]34 int chip_delay;
Wolfgang Grandeggerf1540442009-02-11 18:38:21 +0100[diff] [blame]35 int chip_offset;
36 int chip_nr;
Anton Vorontsov67166032008-06-12 11:10:21 -0500[diff] [blame]37
38 /* no need to fill */
39 int last_ctrl;
Anton Vorontsov6ab97e92008-01-14 23:09:32 +0300[diff] [blame]40};
41
42extern int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun);
43
44#endif