blob: 74a841af4603f34d02cdf58ee7999f6ac48541cd [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Purna Chandra Mandal05bc3f42016-03-21 13:05:42 +05302/*
3 * Microchip PIC32 MUSB "glue layer"
4 *
5 * Copyright (C) 2015, Microchip Technology Inc.
6 * Cristian Birsan <cristian.birsan@microchip.com>
7 * Purna Chandra Mandal <purna.mandal@microchip.com>
8 *
Purna Chandra Mandal05bc3f42016-03-21 13:05:42 +05309 * Based on the dsps "glue layer" code.
10 */
11
12#include <common.h>
Simon Glass9bc15642020-02-03 07:36:16 -070013#include <dm/device_compat.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060014#include <linux/bitops.h>
Simon Glassdbd79542020-05-10 11:40:11 -060015#include <linux/delay.h>
Purna Chandra Mandal05bc3f42016-03-21 13:05:42 +053016#include <linux/usb/musb.h>
17#include "linux-compat.h"
18#include "musb_core.h"
19#include "musb_uboot.h"
20
21DECLARE_GLOBAL_DATA_PTR;
22
23#define PIC32_TX_EP_MASK 0x0f /* EP0 + 7 Tx EPs */
24#define PIC32_RX_EP_MASK 0x0e /* 7 Rx EPs */
25
26#define MUSB_SOFTRST 0x7f
27#define MUSB_SOFTRST_NRST BIT(0)
28#define MUSB_SOFTRST_NRSTX BIT(1)
29
30#define USBCRCON 0
31#define USBCRCON_USBWKUPEN BIT(0) /* Enable Wakeup Interrupt */
32#define USBCRCON_USBRIE BIT(1) /* Enable Remote resume Interrupt */
33#define USBCRCON_USBIE BIT(2) /* Enable USB General interrupt */
34#define USBCRCON_SENDMONEN BIT(3) /* Enable Session End VBUS monitoring */
35#define USBCRCON_BSVALMONEN BIT(4) /* Enable B-Device VBUS monitoring */
36#define USBCRCON_ASVALMONEN BIT(5) /* Enable A-Device VBUS monitoring */
37#define USBCRCON_VBUSMONEN BIT(6) /* Enable VBUS monitoring */
38#define USBCRCON_PHYIDEN BIT(7) /* PHY ID monitoring enable */
39#define USBCRCON_USBIDVAL BIT(8) /* USB ID value */
40#define USBCRCON_USBIDOVEN BIT(9) /* USB ID override enable */
41#define USBCRCON_USBWK BIT(24) /* USB Wakeup Status */
42#define USBCRCON_USBRF BIT(25) /* USB Resume Status */
43#define USBCRCON_USBIF BIT(26) /* USB General Interrupt Status */
44
45/* PIC32 controller data */
46struct pic32_musb_data {
47 struct musb_host_data mdata;
48 struct device dev;
49 void __iomem *musb_glue;
50};
51
52#define to_pic32_musb_data(d) \
53 container_of(d, struct pic32_musb_data, dev)
54
55static void pic32_musb_disable(struct musb *musb)
56{
57 /* no way to shut the controller */
58}
59
60static int pic32_musb_enable(struct musb *musb)
61{
62 /* soft reset by NRSTx */
63 musb_writeb(musb->mregs, MUSB_SOFTRST, MUSB_SOFTRST_NRSTX);
64 /* set mode */
65 musb_platform_set_mode(musb, musb->board_mode);
66
67 return 0;
68}
69
70static irqreturn_t pic32_interrupt(int irq, void *hci)
71{
72 struct musb *musb = hci;
73 irqreturn_t ret = IRQ_NONE;
74 u32 epintr, usbintr;
75
76 /* ack usb core interrupts */
77 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
78 if (musb->int_usb)
79 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
80
81 /* ack endpoint interrupts */
82 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX) & PIC32_RX_EP_MASK;
83 if (musb->int_rx)
84 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
85
86 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX) & PIC32_TX_EP_MASK;
87 if (musb->int_tx)
88 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
89
90 /* drop spurious RX and TX if device is disconnected */
91 if (musb->int_usb & MUSB_INTR_DISCONNECT) {
92 musb->int_tx = 0;
93 musb->int_rx = 0;
94 }
95
96 if (musb->int_tx || musb->int_rx || musb->int_usb)
97 ret = musb_interrupt(musb);
98
99 return ret;
100}
101
102static int pic32_musb_set_mode(struct musb *musb, u8 mode)
103{
104 struct device *dev = musb->controller;
105 struct pic32_musb_data *pdata = to_pic32_musb_data(dev);
106
107 switch (mode) {
108 case MUSB_HOST:
109 clrsetbits_le32(pdata->musb_glue + USBCRCON,
110 USBCRCON_USBIDVAL, USBCRCON_USBIDOVEN);
111 break;
112 case MUSB_PERIPHERAL:
113 setbits_le32(pdata->musb_glue + USBCRCON,
114 USBCRCON_USBIDVAL | USBCRCON_USBIDOVEN);
115 break;
116 case MUSB_OTG:
117 dev_err(dev, "support for OTG is unimplemented\n");
118 break;
119 default:
120 dev_err(dev, "unsupported mode %d\n", mode);
121 return -EINVAL;
122 }
123
124 return 0;
125}
126
127static int pic32_musb_init(struct musb *musb)
128{
129 struct pic32_musb_data *pdata = to_pic32_musb_data(musb->controller);
130 u32 ctrl, hwvers;
131 u8 power;
132
133 /* Returns zero if not clocked */
134 hwvers = musb_read_hwvers(musb->mregs);
135 if (!hwvers)
136 return -ENODEV;
137
138 /* Reset the musb */
139 power = musb_readb(musb->mregs, MUSB_POWER);
140 power = power | MUSB_POWER_RESET;
141 musb_writeb(musb->mregs, MUSB_POWER, power);
142 mdelay(100);
143
144 /* Start the on-chip PHY and its PLL. */
145 power = power & ~MUSB_POWER_RESET;
146 musb_writeb(musb->mregs, MUSB_POWER, power);
147
148 musb->isr = pic32_interrupt;
149
150 ctrl = USBCRCON_USBIF | USBCRCON_USBRF |
151 USBCRCON_USBWK | USBCRCON_USBIDOVEN |
152 USBCRCON_PHYIDEN | USBCRCON_USBIE |
153 USBCRCON_USBRIE | USBCRCON_USBWKUPEN |
154 USBCRCON_VBUSMONEN;
155 writel(ctrl, pdata->musb_glue + USBCRCON);
156
157 return 0;
158}
159
160/* PIC32 supports only 32bit read operation */
161void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
162{
163 void __iomem *fifo = hw_ep->fifo;
164 u32 val, rem = len % 4;
165
166 /* USB stack ensures dst is always 32bit aligned. */
167 readsl(fifo, dst, len / 4);
168 if (rem) {
169 dst += len & ~0x03;
170 val = musb_readl(fifo, 0);
171 memcpy(dst, &val, rem);
172 }
173}
174
175const struct musb_platform_ops pic32_musb_ops = {
176 .init = pic32_musb_init,
177 .set_mode = pic32_musb_set_mode,
178 .disable = pic32_musb_disable,
179 .enable = pic32_musb_enable,
180};
181
182/* PIC32 default FIFO config - fits in 8KB */
183static struct musb_fifo_cfg pic32_musb_fifo_config[] = {
184 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
185 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
186 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
187 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
188 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
189 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
190 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
191 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
192 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
193 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
194 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
195 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
196 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
197 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
198};
199
200static struct musb_hdrc_config pic32_musb_config = {
201 .fifo_cfg = pic32_musb_fifo_config,
202 .fifo_cfg_size = ARRAY_SIZE(pic32_musb_fifo_config),
203 .multipoint = 1,
204 .dyn_fifo = 1,
205 .num_eps = 8,
206 .ram_bits = 11,
207};
208
209/* PIC32 has one MUSB controller which can be host or gadget */
210static struct musb_hdrc_platform_data pic32_musb_plat = {
211 .mode = MUSB_HOST,
212 .config = &pic32_musb_config,
213 .power = 250, /* 500mA */
214 .platform_ops = &pic32_musb_ops,
215};
216
217static int musb_usb_probe(struct udevice *dev)
218{
219 struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
220 struct pic32_musb_data *pdata = dev_get_priv(dev);
221 struct musb_host_data *mdata = &pdata->mdata;
222 struct fdt_resource mc, glue;
223 void *fdt = (void *)gd->fdt_blob;
Simon Glassdd79d6e2017-01-17 16:52:55 -0700224 int node = dev_of_offset(dev);
Purna Chandra Mandal05bc3f42016-03-21 13:05:42 +0530225 void __iomem *mregs;
226 int ret;
227
228 priv->desc_before_addr = true;
229
230 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
231 "mc", &mc);
232 if (ret < 0) {
233 printf("pic32-musb: resource \"mc\" not found\n");
234 return ret;
235 }
236
237 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
238 "control", &glue);
239 if (ret < 0) {
240 printf("pic32-musb: resource \"control\" not found\n");
241 return ret;
242 }
243
244 mregs = ioremap(mc.start, fdt_resource_size(&mc));
245 pdata->musb_glue = ioremap(glue.start, fdt_resource_size(&glue));
246
247 /* init controller */
248#ifdef CONFIG_USB_MUSB_HOST
249 mdata->host = musb_init_controller(&pic32_musb_plat,
250 &pdata->dev, mregs);
251 if (!mdata->host)
252 return -EIO;
253
254 ret = musb_lowlevel_init(mdata);
255#else
256 pic32_musb_plat.mode = MUSB_PERIPHERAL;
Jagan Tekif0a6d792018-07-20 12:43:56 +0530257 mdata->host = musb_register(&pic32_musb_plat, &pdata->dev, mregs);
258 if (!mdata->host)
259 return -EIO;
Purna Chandra Mandal05bc3f42016-03-21 13:05:42 +0530260#endif
Jagan Tekif0a6d792018-07-20 12:43:56 +0530261 if ((ret == 0) && mdata->host)
Purna Chandra Mandal05bc3f42016-03-21 13:05:42 +0530262 printf("PIC32 MUSB OTG\n");
263
264 return ret;
265}
266
267static int musb_usb_remove(struct udevice *dev)
268{
269 struct pic32_musb_data *pdata = dev_get_priv(dev);
270
271 musb_stop(pdata->mdata.host);
272
273 return 0;
274}
275
276static const struct udevice_id pic32_musb_ids[] = {
277 { .compatible = "microchip,pic32mzda-usb" },
278 { }
279};
280
281U_BOOT_DRIVER(usb_musb) = {
282 .name = "pic32-musb",
283 .id = UCLASS_USB,
284 .of_match = pic32_musb_ids,
285 .probe = musb_usb_probe,
286 .remove = musb_usb_remove,
287#ifdef CONFIG_USB_MUSB_HOST
288 .ops = &musb_usb_ops,
289#endif
290 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
291 .priv_auto_alloc_size = sizeof(struct pic32_musb_data),
292};