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Masahiro Yamadaedbecf52015-08-28 22:33:15 +09001/*
2 * Device Tree Source for UniPhier ProXstream2 SoC
3 *
4 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+ X11
7 */
8
Masahiro Yamada3de725b2015-12-16 10:54:07 +09009/include/ "uniphier-common32.dtsi"
Masahiro Yamadaedbecf52015-08-28 22:33:15 +090010
11/ {
12 compatible = "socionext,proxstream2";
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17 enable-method = "socionext,uniphier-smp";
18
19 cpu@0 {
20 device_type = "cpu";
21 compatible = "arm,cortex-a9";
22 reg = <0>;
Masahiro Yamadab36f3052015-12-16 10:54:08 +090023 next-level-cache = <&l2>;
Masahiro Yamadaedbecf52015-08-28 22:33:15 +090024 };
25
26 cpu@1 {
27 device_type = "cpu";
28 compatible = "arm,cortex-a9";
29 reg = <1>;
Masahiro Yamadab36f3052015-12-16 10:54:08 +090030 next-level-cache = <&l2>;
Masahiro Yamadaedbecf52015-08-28 22:33:15 +090031 };
32
33 cpu@2 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a9";
36 reg = <2>;
Masahiro Yamadab36f3052015-12-16 10:54:08 +090037 next-level-cache = <&l2>;
Masahiro Yamadaedbecf52015-08-28 22:33:15 +090038 };
39
40 cpu@3 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a9";
43 reg = <3>;
Masahiro Yamadab36f3052015-12-16 10:54:08 +090044 next-level-cache = <&l2>;
Masahiro Yamadaedbecf52015-08-28 22:33:15 +090045 };
46 };
47
48 clocks {
49 arm_timer_clk: arm_timer_clk {
50 #clock-cells = <0>;
51 compatible = "fixed-clock";
52 clock-frequency = <50000000>;
53 };
54
55 uart_clk: uart_clk {
56 #clock-cells = <0>;
57 compatible = "fixed-clock";
58 clock-frequency = <88900000>;
59 };
60
61 i2c_clk: i2c_clk {
62 #clock-cells = <0>;
63 compatible = "fixed-clock";
64 clock-frequency = <50000000>;
65 };
66 };
Masahiro Yamada3de725b2015-12-16 10:54:07 +090067};
Masahiro Yamadaedbecf52015-08-28 22:33:15 +090068
Masahiro Yamada3de725b2015-12-16 10:54:07 +090069&soc {
Masahiro Yamadab36f3052015-12-16 10:54:08 +090070 l2: l2-cache@500c0000 {
71 compatible = "socionext,uniphier-system-cache";
72 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
73 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
74 cache-unified;
75 cache-size = <(1280 * 1024)>;
76 cache-sets = <512>;
77 cache-line-size = <128>;
78 cache-level = <2>;
79 };
80
Masahiro Yamada3de725b2015-12-16 10:54:07 +090081 i2c0: i2c@58780000 {
82 compatible = "socionext,uniphier-fi2c";
83 status = "disabled";
84 reg = <0x58780000 0x80>;
Masahiro Yamadaedbecf52015-08-28 22:33:15 +090085 #address-cells = <1>;
Masahiro Yamada3de725b2015-12-16 10:54:07 +090086 #size-cells = <0>;
87 interrupts = <0 41 4>;
88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_i2c0>;
90 clocks = <&i2c_clk>;
91 clock-frequency = <100000>;
92 };
Masahiro Yamadaedbecf52015-08-28 22:33:15 +090093
Masahiro Yamada3de725b2015-12-16 10:54:07 +090094 i2c1: i2c@58781000 {
95 compatible = "socionext,uniphier-fi2c";
96 status = "disabled";
97 reg = <0x58781000 0x80>;
98 #address-cells = <1>;
99 #size-cells = <0>;
100 interrupts = <0 42 4>;
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_i2c1>;
103 clocks = <&i2c_clk>;
104 clock-frequency = <100000>;
105 };
Masahiro Yamadaedbecf52015-08-28 22:33:15 +0900106
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900107 i2c2: i2c@58782000 {
108 compatible = "socionext,uniphier-fi2c";
109 status = "disabled";
110 reg = <0x58782000 0x80>;
111 #address-cells = <1>;
112 #size-cells = <0>;
113 pinctrl-names = "default";
114 pinctrl-0 = <&pinctrl_i2c2>;
115 interrupts = <0 43 4>;
116 clocks = <&i2c_clk>;
117 clock-frequency = <100000>;
118 };
Masahiro Yamadaedbecf52015-08-28 22:33:15 +0900119
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900120 i2c3: i2c@58783000 {
121 compatible = "socionext,uniphier-fi2c";
122 status = "disabled";
123 reg = <0x58783000 0x80>;
124 #address-cells = <1>;
125 #size-cells = <0>;
126 interrupts = <0 44 4>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_i2c3>;
129 clocks = <&i2c_clk>;
130 clock-frequency = <100000>;
131 };
Masahiro Yamadaedbecf52015-08-28 22:33:15 +0900132
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900133 /* chip-internal connection for DMD */
134 i2c4: i2c@58784000 {
135 compatible = "socionext,uniphier-fi2c";
136 reg = <0x58784000 0x80>;
137 #address-cells = <1>;
138 #size-cells = <0>;
139 interrupts = <0 45 4>;
140 clocks = <&i2c_clk>;
141 clock-frequency = <400000>;
142 };
Masahiro Yamadaedbecf52015-08-28 22:33:15 +0900143
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900144 /* chip-internal connection for STM */
145 i2c5: i2c@58785000 {
146 compatible = "socionext,uniphier-fi2c";
147 reg = <0x58785000 0x80>;
148 #address-cells = <1>;
149 #size-cells = <0>;
150 interrupts = <0 25 4>;
151 clocks = <&i2c_clk>;
152 clock-frequency = <400000>;
153 };
Masahiro Yamadaedbecf52015-08-28 22:33:15 +0900154
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900155 /* chip-internal connection for HDMI */
156 i2c6: i2c@58786000 {
157 compatible = "socionext,uniphier-fi2c";
158 reg = <0x58786000 0x80>;
159 #address-cells = <1>;
160 #size-cells = <0>;
161 interrupts = <0 26 4>;
162 clocks = <&i2c_clk>;
163 clock-frequency = <400000>;
164 };
Masahiro Yamadaedbecf52015-08-28 22:33:15 +0900165
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900166 usb0: usb@65a00000 {
167 compatible = "socionext,uniphier-xhci", "generic-xhci";
168 status = "disabled";
169 reg = <0x65a00000 0x100>;
Masahiro Yamadab36f3052015-12-16 10:54:08 +0900170 interrupts = <0 134 4>;
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900171 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900173 };
Masahiro Yamadaedbecf52015-08-28 22:33:15 +0900174
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900175 usb1: usb@65c00000 {
176 compatible = "socionext,uniphier-xhci", "generic-xhci";
177 status = "disabled";
178 reg = <0x65c00000 0x100>;
Masahiro Yamadab36f3052015-12-16 10:54:08 +0900179 interrupts = <0 137 4>;
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900182 };
183};
Masahiro Yamadaedbecf52015-08-28 22:33:15 +0900184
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900185&serial0 {
186 clock-frequency = <88900000>;
187};
Masahiro Yamadaedbecf52015-08-28 22:33:15 +0900188
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900189&serial1 {
190 clock-frequency = <88900000>;
191};
Masahiro Yamadaa4e54cc2015-11-04 21:56:07 +0900192
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900193&serial2 {
194 clock-frequency = <88900000>;
195};
Masahiro Yamadaa4e54cc2015-11-04 21:56:07 +0900196
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900197&serial3 {
198 clock-frequency = <88900000>;
Masahiro Yamadaedbecf52015-08-28 22:33:15 +0900199};
200
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900201&pinctrl {
202 compatible = "socionext,proxstream2-pinctrl", "syscon";
203};