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git01.mediatek.com / filogic / uboot / b35aa4f7b4ddadb58b2c20e407a95f1480e618b9 / . / dts / upstream / src / powerpc / xpedite5330.dts
blob: e8fc90c52ad6bedaf7acba759fc6ad55661d01d2 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2008 Extreme Engineering Solutions, Inc.
4 * Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
5 *
6 * XPedite5330 3U CompactPCI module based on MPC8572E
7 */
8
9/dts-v1/;
10/ {
11 model = "xes,xpedite5330";
12 compatible = "xes,xpedite5330", "xes,MPC8572";
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "3U CompactPCI";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
17
18 aliases {
19 ethernet0 = &enet0;
20 ethernet1 = &enet1;
21 serial0 = &serial0;
22 serial1 = &serial1;
23 pci0 = &pci0;
24 pci1 = &pci1;
25 pci2 = &pci2;
26 };
27
28 pmcslots {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 pmcslot@0 {
33 cell-index = <0>;
34 /*
35 * boolean properties (true if defined):
36 * monarch;
37 * module-present;
38 */
39 };
40 };
41
42 xmcslots {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
46 xmcslot@0 {
47 cell-index = <0>;
48 /*
49 * boolean properties (true if defined):
50 * module-present;
51 */
52 };
53 };
54
55 cpci {
56 /*
57 * boolean properties (true if defined):
58 * system-controller;
59 */
60 system-controller;
61 };
62
63 cpus {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 PowerPC,8572@0 {
68 device_type = "cpu";
69 reg = <0x0>;
70 d-cache-line-size = <32>; // 32 bytes
71 i-cache-line-size = <32>; // 32 bytes
72 d-cache-size = <0x8000>; // L1, 32K
73 i-cache-size = <0x8000>; // L1, 32K
74 timebase-frequency = <0>;
75 bus-frequency = <0>;
76 clock-frequency = <0>;
77 next-level-cache = <&L2>;
78 };
79
80 PowerPC,8572@1 {
81 device_type = "cpu";
82 reg = <0x1>;
83 d-cache-line-size = <32>; // 32 bytes
84 i-cache-line-size = <32>; // 32 bytes
85 d-cache-size = <0x8000>; // L1, 32K
86 i-cache-size = <0x8000>; // L1, 32K
87 timebase-frequency = <0>;
88 bus-frequency = <0>;
89 clock-frequency = <0>;
90 next-level-cache = <&L2>;
91 };
92 };
93
94 memory {
95 device_type = "memory";
96 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
97 };
98
99 localbus@ef005000 {
100 #address-cells = <2>;
101 #size-cells = <1>;
102 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
103 reg = <0 0xef005000 0 0x1000>;
104 interrupts = <19 2>;
105 interrupt-parent = <&mpic>;
106 /* Local bus region mappings */
107 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
108 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
109 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
110 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
111
112 nor-boot@0,0 {
113 compatible = "amd,s29gl01gp", "cfi-flash";
114 bank-width = <2>;
115 reg = <0 0 0x8000000>; /* 128MB */
116 #address-cells = <1>;
117 #size-cells = <1>;
118 partition@0 {
119 label = "Primary user space";
120 reg = <0x00000000 0x6f00000>; /* 111 MB */
121 };
122 partition@6f00000 {
123 label = "Primary kernel";
124 reg = <0x6f00000 0x1000000>; /* 16 MB */
125 };
126 partition@7f00000 {
127 label = "Primary DTB";
128 reg = <0x7f00000 0x40000>; /* 256 KB */
129 };
130 partition@7f40000 {
131 label = "Primary U-Boot environment";
132 reg = <0x7f40000 0x40000>; /* 256 KB */
133 };
134 partition@7f80000 {
135 label = "Primary U-Boot";
136 reg = <0x7f80000 0x80000>; /* 512 KB */
137 read-only;
138 };
139 };
140
141 nor-alternate@1,0 {
142 compatible = "amd,s29gl01gp", "cfi-flash";
143 bank-width = <2>;
144 //reg = <0xf0000000 0x08000000>; /* 128MB */
145 reg = <1 0 0x8000000>; /* 128MB */
146 #address-cells = <1>;
147 #size-cells = <1>;
148 partition@0 {
149 label = "Secondary user space";
150 reg = <0x00000000 0x6f00000>; /* 111 MB */
151 };
152 partition@6f00000 {
153 label = "Secondary kernel";
154 reg = <0x6f00000 0x1000000>; /* 16 MB */
155 };
156 partition@7f00000 {
157 label = "Secondary DTB";
158 reg = <0x7f00000 0x40000>; /* 256 KB */
159 };
160 partition@7f40000 {
161 label = "Secondary U-Boot environment";
162 reg = <0x7f40000 0x40000>; /* 256 KB */
163 };
164 partition@7f80000 {
165 label = "Secondary U-Boot";
166 reg = <0x7f80000 0x80000>; /* 512 KB */
167 read-only;
168 };
169 };
170
171 nand@2,0 {
172 #address-cells = <1>;
173 #size-cells = <1>;
174 /*
175 * Actual part could be ST Micro NAND08GW3B2A (1 GB),
176 * Micron MT29F8G08DAA (2x 512 MB), or Micron
177 * MT29F16G08FAA (2x 1 GB), depending on the build
178 * configuration
179 */
180 compatible = "fsl,mpc8572-fcm-nand",
181 "fsl,elbc-fcm-nand";
182 reg = <2 0 0x40000>;
183 /* U-Boot should fix this up if chip size > 1 GB */
184 partition@0 {
185 label = "NAND Filesystem";
186 reg = <0 0x40000000>;
187 };
188 };
189
190 };
191
192 soc8572@ef000000 {
193 #address-cells = <1>;
194 #size-cells = <1>;
195 device_type = "soc";
196 compatible = "fsl,mpc8572-immr", "simple-bus";
197 ranges = <0x0 0 0xef000000 0x100000>;
198 bus-frequency = <0>; // Filled out by uboot.
199
200 ecm-law@0 {
201 compatible = "fsl,ecm-law";
202 reg = <0x0 0x1000>;
203 fsl,num-laws = <12>;
204 };
205
206 ecm@1000 {
207 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
208 reg = <0x1000 0x1000>;
209 interrupts = <17 2>;
210 interrupt-parent = <&mpic>;
211 };
212
213 memory-controller@2000 {
214 compatible = "fsl,mpc8572-memory-controller";
215 reg = <0x2000 0x1000>;
216 interrupt-parent = <&mpic>;
217 interrupts = <18 2>;
218 };
219
220 memory-controller@6000 {
221 compatible = "fsl,mpc8572-memory-controller";
222 reg = <0x6000 0x1000>;
223 interrupt-parent = <&mpic>;
224 interrupts = <18 2>;
225 };
226
227 L2: l2-cache-controller@20000 {
228 compatible = "fsl,mpc8572-l2-cache-controller";
229 reg = <0x20000 0x1000>;
230 cache-line-size = <32>; // 32 bytes
231 cache-size = <0x100000>; // L2, 1M
232 interrupt-parent = <&mpic>;
233 interrupts = <16 2>;
234 };
235
236 i2c@3000 {
237 #address-cells = <1>;
238 #size-cells = <0>;
239 cell-index = <0>;
240 compatible = "fsl-i2c";
241 reg = <0x3000 0x100>;
242 interrupts = <43 2>;
243 interrupt-parent = <&mpic>;
244 dfsrr;
245
246 temp-sensor@48 {
247 compatible = "dallas,ds1631", "dallas,ds1621";
248 reg = <0x48>;
249 };
250
251 temp-sensor@4c {
252 compatible = "adi,adt7461";
253 reg = <0x4c>;
254 };
255
256 cpu-supervisor@51 {
257 compatible = "dallas,ds4510";
258 reg = <0x51>;
259 };
260
261 eeprom@54 {
262 compatible = "atmel,at24c128b";
263 reg = <0x54>;
264 };
265
266 rtc@68 {
267 compatible = "st,m41t00",
268 "dallas,ds1338";
269 reg = <0x68>;
270 };
271
272 pcie-switch@70 {
273 compatible = "plx,pex8518";
274 reg = <0x70>;
275 };
276
277 gpio1: gpio@18 {
278 compatible = "nxp,pca9557";
279 reg = <0x18>;
280 #gpio-cells = <2>;
281 gpio-controller;
282 polarity = <0x00>;
283 };
284
285 gpio2: gpio@1c {
286 compatible = "nxp,pca9557";
287 reg = <0x1c>;
288 #gpio-cells = <2>;
289 gpio-controller;
290 polarity = <0x00>;
291 };
292
293 gpio3: gpio@1e {
294 compatible = "nxp,pca9557";
295 reg = <0x1e>;
296 #gpio-cells = <2>;
297 gpio-controller;
298 polarity = <0x00>;
299 };
300
301 gpio4: gpio@1f {
302 compatible = "nxp,pca9557";
303 reg = <0x1f>;
304 #gpio-cells = <2>;
305 gpio-controller;
306 polarity = <0x00>;
307 };
308 };
309
310 i2c@3100 {
311 #address-cells = <1>;
312 #size-cells = <0>;
313 cell-index = <1>;
314 compatible = "fsl-i2c";
315 reg = <0x3100 0x100>;
316 interrupts = <43 2>;
317 interrupt-parent = <&mpic>;
318 dfsrr;
319 };
320
321 dma@c300 {
322 #address-cells = <1>;
323 #size-cells = <1>;
324 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
325 reg = <0xc300 0x4>;
326 ranges = <0x0 0xc100 0x200>;
327 cell-index = <1>;
328 dma-channel@0 {
329 compatible = "fsl,mpc8572-dma-channel",
330 "fsl,eloplus-dma-channel";
331 reg = <0x0 0x80>;
332 cell-index = <0>;
333 interrupt-parent = <&mpic>;
334 interrupts = <76 2>;
335 };
336 dma-channel@80 {
337 compatible = "fsl,mpc8572-dma-channel",
338 "fsl,eloplus-dma-channel";
339 reg = <0x80 0x80>;
340 cell-index = <1>;
341 interrupt-parent = <&mpic>;
342 interrupts = <77 2>;
343 };
344 dma-channel@100 {
345 compatible = "fsl,mpc8572-dma-channel",
346 "fsl,eloplus-dma-channel";
347 reg = <0x100 0x80>;
348 cell-index = <2>;
349 interrupt-parent = <&mpic>;
350 interrupts = <78 2>;
351 };
352 dma-channel@180 {
353 compatible = "fsl,mpc8572-dma-channel",
354 "fsl,eloplus-dma-channel";
355 reg = <0x180 0x80>;
356 cell-index = <3>;
357 interrupt-parent = <&mpic>;
358 interrupts = <79 2>;
359 };
360 };
361
362 dma@21300 {
363 #address-cells = <1>;
364 #size-cells = <1>;
365 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
366 reg = <0x21300 0x4>;
367 ranges = <0x0 0x21100 0x200>;
368 cell-index = <0>;
369 dma-channel@0 {
370 compatible = "fsl,mpc8572-dma-channel",
371 "fsl,eloplus-dma-channel";
372 reg = <0x0 0x80>;
373 cell-index = <0>;
374 interrupt-parent = <&mpic>;
375 interrupts = <20 2>;
376 };
377 dma-channel@80 {
378 compatible = "fsl,mpc8572-dma-channel",
379 "fsl,eloplus-dma-channel";
380 reg = <0x80 0x80>;
381 cell-index = <1>;
382 interrupt-parent = <&mpic>;
383 interrupts = <21 2>;
384 };
385 dma-channel@100 {
386 compatible = "fsl,mpc8572-dma-channel",
387 "fsl,eloplus-dma-channel";
388 reg = <0x100 0x80>;
389 cell-index = <2>;
390 interrupt-parent = <&mpic>;
391 interrupts = <22 2>;
392 };
393 dma-channel@180 {
394 compatible = "fsl,mpc8572-dma-channel",
395 "fsl,eloplus-dma-channel";
396 reg = <0x180 0x80>;
397 cell-index = <3>;
398 interrupt-parent = <&mpic>;
399 interrupts = <23 2>;
400 };
401 };
402
403 /* eTSEC 1 */
404 enet0: ethernet@24000 {
405 #address-cells = <1>;
406 #size-cells = <1>;
407 cell-index = <0>;
408 device_type = "network";
409 model = "eTSEC";
410 compatible = "gianfar";
411 reg = <0x24000 0x1000>;
412 ranges = <0x0 0x24000 0x1000>;
413 local-mac-address = [ 00 00 00 00 00 00 ];
414 interrupts = <29 2 30 2 34 2>;
415 interrupt-parent = <&mpic>;
416 tbi-handle = <&tbi0>;
417 phy-handle = <&phy0>;
418 phy-connection-type = "sgmii";
419
420 mdio@520 {
421 #address-cells = <1>;
422 #size-cells = <0>;
423 compatible = "fsl,gianfar-mdio";
424 reg = <0x520 0x20>;
425
426 phy0: ethernet-phy@1 {
427 interrupt-parent = <&mpic>;
428 interrupts = <8 1>;
429 reg = <0x1>;
430 };
431 phy1: ethernet-phy@2 {
432 interrupt-parent = <&mpic>;
433 interrupts = <8 1>;
434 reg = <0x2>;
435 };
436 tbi0: tbi-phy@11 {
437 reg = <0x11>;
438 device_type = "tbi-phy";
439 };
440 };
441 };
442
443 /* eTSEC 2 */
444 enet1: ethernet@25000 {
445 #address-cells = <1>;
446 #size-cells = <1>;
447 cell-index = <1>;
448 device_type = "network";
449 model = "eTSEC";
450 compatible = "gianfar";
451 reg = <0x25000 0x1000>;
452 ranges = <0x0 0x25000 0x1000>;
453 local-mac-address = [ 00 00 00 00 00 00 ];
454 interrupts = <35 2 36 2 40 2>;
455 interrupt-parent = <&mpic>;
456 tbi-handle = <&tbi1>;
457 phy-handle = <&phy1>;
458 phy-connection-type = "sgmii";
459
460 mdio@520 {
461 #address-cells = <1>;
462 #size-cells = <0>;
463 compatible = "fsl,gianfar-tbi";
464 reg = <0x520 0x20>;
465
466 tbi1: tbi-phy@11 {
467 reg = <0x11>;
468 device_type = "tbi-phy";
469 };
470 };
471 };
472
473 /* UART0 */
474 serial0: serial@4500 {
475 cell-index = <0>;
476 device_type = "serial";
477 compatible = "fsl,ns16550", "ns16550";
478 reg = <0x4500 0x100>;
479 clock-frequency = <0>;
480 interrupts = <42 2>;
481 interrupt-parent = <&mpic>;
482 };
483
484 /* UART1 */
485 serial1: serial@4600 {
486 cell-index = <1>;
487 device_type = "serial";
488 compatible = "fsl,ns16550", "ns16550";
489 reg = <0x4600 0x100>;
490 clock-frequency = <0>;
491 interrupts = <42 2>;
492 interrupt-parent = <&mpic>;
493 };
494
495 global-utilities@e0000 { //global utilities block
496 compatible = "fsl,mpc8572-guts";
497 reg = <0xe0000 0x1000>;
498 fsl,has-rstcr;
499 };
500
501 msi@41600 {
502 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
503 reg = <0x41600 0x80>;
504 msi-available-ranges = <0 0x100>;
505 interrupts = <
506 0xe0 0
507 0xe1 0
508 0xe2 0
509 0xe3 0
510 0xe4 0
511 0xe5 0
512 0xe6 0
513 0xe7 0>;
514 interrupt-parent = <&mpic>;
515 };
516
517 crypto@30000 {
518 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
519 "fsl,sec2.1", "fsl,sec2.0";
520 reg = <0x30000 0x10000>;
521 interrupts = <45 2 58 2>;
522 interrupt-parent = <&mpic>;
523 fsl,num-channels = <4>;
524 fsl,channel-fifo-len = <24>;
525 fsl,exec-units-mask = <0x9fe>;
526 fsl,descriptor-types-mask = <0x3ab0ebf>;
527 };
528
529 mpic: pic@40000 {
530 interrupt-controller;
531 #address-cells = <0>;
532 #interrupt-cells = <2>;
533 reg = <0x40000 0x40000>;
534 compatible = "chrp,open-pic";
535 device_type = "open-pic";
536 };
537
538 gpio0: gpio@f000 {
539 compatible = "fsl,mpc8572-gpio";
540 reg = <0xf000 0x1000>;
541 interrupts = <47 2>;
542 interrupt-parent = <&mpic>;
543 #gpio-cells = <2>;
544 gpio-controller;
545 };
546
547 gpio-leds {
548 compatible = "gpio-leds";
549
550 heartbeat {
551 label = "Heartbeat";
552 gpios = <&gpio0 4 1>;
553 linux,default-trigger = "heartbeat";
554 };
555
556 yellow {
557 label = "Yellow";
558 gpios = <&gpio0 5 1>;
559 };
560
561 red {
562 label = "Red";
563 gpios = <&gpio0 6 1>;
564 };
565
566 green {
567 label = "Green";
568 gpios = <&gpio0 7 1>;
569 };
570 };
571
572 /* PME (pattern-matcher) */
573 pme@10000 {
574 compatible = "fsl,mpc8572-pme", "pme8572";
575 reg = <0x10000 0x5000>;
576 interrupts = <57 2 64 2 65 2 66 2 67 2>;
577 interrupt-parent = <&mpic>;
578 };
579
580 tlu@2f000 {
581 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
582 reg = <0x2f000 0x1000>;
583 interrupts = <61 2>;
584 interrupt-parent = <&mpic>;
585 };
586
587 tlu@15000 {
588 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
589 reg = <0x15000 0x1000>;
590 interrupts = <75 2>;
591 interrupt-parent = <&mpic>;
592 };
593 };
594
595 /* PCI Express controller 3 - CompactPCI bus via PEX8112 bridge */
596 pci0: pcie@ef008000 {
597 compatible = "fsl,mpc8548-pcie";
598 device_type = "pci";
599 #interrupt-cells = <1>;
600 #size-cells = <2>;
601 #address-cells = <3>;
602 reg = <0 0xef008000 0 0x1000>;
603 bus-range = <0 255>;
604 ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x10000000
605 0x1000000 0x0 0x00000000 0 0xe9000000 0x0 0x10000>;
606 clock-frequency = <33333333>;
607 interrupt-parent = <&mpic>;
608 interrupts = <24 2>;
609 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
610 interrupt-map = <
611 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
612 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
613 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
614 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
615 >;
616 pcie@0 {
617 reg = <0x0 0x0 0x0 0x0 0x0>;
618 #size-cells = <2>;
619 #address-cells = <3>;
620 device_type = "pci";
621 ranges = <0x02000000 0x0 0xe0000000
622 0x02000000 0x0 0xe0000000
623 0x0 0x10000000
624
625 0x01000000 0x0 0x0
626 0x01000000 0x0 0x0
627 0x0 0x100000>;
628 };
629 };
630
631 /* PCI Express controller 2, PMC module via PEX8112 bridge */
632 pci1: pcie@ef009000 {
633 compatible = "fsl,mpc8548-pcie";
634 device_type = "pci";
635 #interrupt-cells = <1>;
636 #size-cells = <2>;
637 #address-cells = <3>;
638 reg = <0 0xef009000 0 0x1000>;
639 bus-range = <0 255>;
640 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
641 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x10000>;
642 clock-frequency = <33333333>;
643 interrupt-parent = <&mpic>;
644 interrupts = <25 2>;
645 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
646 interrupt-map = <
647 /* IDSEL 0x0 */
648 0x0 0x0 0x0 0x1 &mpic 0x4 0x1
649 0x0 0x0 0x0 0x2 &mpic 0x5 0x1
650 0x0 0x0 0x0 0x3 &mpic 0x6 0x1
651 0x0 0x0 0x0 0x4 &mpic 0x7 0x1
652 >;
653 pcie@0 {
654 reg = <0x0 0x0 0x0 0x0 0x0>;
655 #size-cells = <2>;
656 #address-cells = <3>;
657 device_type = "pci";
658 ranges = <0x2000000 0x0 0xc0000000
659 0x2000000 0x0 0xc0000000
660 0x0 0x10000000
661
662 0x1000000 0x0 0x0
663 0x1000000 0x0 0x0
664 0x0 0x100000>;
665 };
666 };
667
668 /* PCI Express controller 1, XMC P15 */
669 pci2: pcie@ef00a000 {
670 compatible = "fsl,mpc8548-pcie";
671 device_type = "pci";
672 #interrupt-cells = <1>;
673 #size-cells = <2>;
674 #address-cells = <3>;
675 reg = <0 0xef00a000 0 0x1000>;
676 bus-range = <0 255>;
677 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
678 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
679 clock-frequency = <33333333>;
680 interrupt-parent = <&mpic>;
681 interrupts = <26 2>;
682 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
683 interrupt-map = <
684 /* IDSEL 0x0 */
685 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
686 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
687 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
688 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
689 >;
690 pcie@0 {
691 reg = <0x0 0x0 0x0 0x0 0x0>;
692 #size-cells = <2>;
693 #address-cells = <3>;
694 device_type = "pci";
695 ranges = <0x2000000 0x0 0x80000000
696 0x2000000 0x0 0x80000000
697 0x0 0x40000000
698
699 0x1000000 0x0 0x0
700 0x1000000 0x0 0x0
701 0x0 0x100000>;
702 };
703 };
704};