Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | /* |
| 3 | * TQM 8541 Device Tree Source |
| 4 | * |
| 5 | * Copyright 2008 Freescale Semiconductor Inc. |
| 6 | */ |
| 7 | |
| 8 | /dts-v1/; |
| 9 | |
| 10 | /include/ "fsl/e500v1_power_isa.dtsi" |
| 11 | |
| 12 | / { |
| 13 | model = "tqc,tqm8541"; |
| 14 | compatible = "tqc,tqm8541"; |
| 15 | #address-cells = <1>; |
| 16 | #size-cells = <1>; |
| 17 | |
| 18 | aliases { |
| 19 | ethernet0 = &enet0; |
| 20 | ethernet1 = &enet1; |
| 21 | serial0 = &serial0; |
| 22 | serial1 = &serial1; |
| 23 | pci0 = &pci0; |
| 24 | }; |
| 25 | |
| 26 | cpus { |
| 27 | #address-cells = <1>; |
| 28 | #size-cells = <0>; |
| 29 | |
| 30 | PowerPC,8541@0 { |
| 31 | device_type = "cpu"; |
| 32 | reg = <0>; |
| 33 | d-cache-line-size = <32>; |
| 34 | i-cache-line-size = <32>; |
| 35 | d-cache-size = <32768>; |
| 36 | i-cache-size = <32768>; |
| 37 | timebase-frequency = <0>; |
| 38 | bus-frequency = <0>; |
| 39 | clock-frequency = <0>; |
| 40 | next-level-cache = <&L2>; |
| 41 | }; |
| 42 | }; |
| 43 | |
| 44 | memory { |
| 45 | device_type = "memory"; |
| 46 | reg = <0x00000000 0x10000000>; |
| 47 | }; |
| 48 | |
| 49 | soc@e0000000 { |
| 50 | #address-cells = <1>; |
| 51 | #size-cells = <1>; |
| 52 | device_type = "soc"; |
| 53 | ranges = <0x0 0xe0000000 0x100000>; |
| 54 | bus-frequency = <0>; |
| 55 | compatible = "fsl,mpc8541-immr", "simple-bus"; |
| 56 | |
| 57 | ecm-law@0 { |
| 58 | compatible = "fsl,ecm-law"; |
| 59 | reg = <0x0 0x1000>; |
| 60 | fsl,num-laws = <8>; |
| 61 | }; |
| 62 | |
| 63 | ecm@1000 { |
| 64 | compatible = "fsl,mpc8541-ecm", "fsl,ecm"; |
| 65 | reg = <0x1000 0x1000>; |
| 66 | interrupts = <17 2>; |
| 67 | interrupt-parent = <&mpic>; |
| 68 | }; |
| 69 | |
| 70 | memory-controller@2000 { |
| 71 | compatible = "fsl,mpc8540-memory-controller"; |
| 72 | reg = <0x2000 0x1000>; |
| 73 | interrupt-parent = <&mpic>; |
| 74 | interrupts = <18 2>; |
| 75 | }; |
| 76 | |
| 77 | L2: l2-cache-controller@20000 { |
| 78 | compatible = "fsl,mpc8540-l2-cache-controller"; |
| 79 | reg = <0x20000 0x1000>; |
| 80 | cache-line-size = <32>; |
| 81 | cache-size = <0x40000>; // L2, 256K |
| 82 | interrupt-parent = <&mpic>; |
| 83 | interrupts = <16 2>; |
| 84 | }; |
| 85 | |
| 86 | i2c@3000 { |
| 87 | #address-cells = <1>; |
| 88 | #size-cells = <0>; |
| 89 | cell-index = <0>; |
| 90 | compatible = "fsl-i2c"; |
| 91 | reg = <0x3000 0x100>; |
| 92 | interrupts = <43 2>; |
| 93 | interrupt-parent = <&mpic>; |
| 94 | dfsrr; |
| 95 | |
| 96 | dtt@48 { |
| 97 | compatible = "national,lm75"; |
| 98 | reg = <0x48>; |
| 99 | }; |
| 100 | |
| 101 | rtc@68 { |
| 102 | compatible = "dallas,ds1337"; |
| 103 | reg = <0x68>; |
| 104 | }; |
| 105 | }; |
| 106 | |
| 107 | dma@21300 { |
| 108 | #address-cells = <1>; |
| 109 | #size-cells = <1>; |
| 110 | compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma"; |
| 111 | reg = <0x21300 0x4>; |
| 112 | ranges = <0x0 0x21100 0x200>; |
| 113 | cell-index = <0>; |
| 114 | dma-channel@0 { |
| 115 | compatible = "fsl,mpc8541-dma-channel", |
| 116 | "fsl,eloplus-dma-channel"; |
| 117 | reg = <0x0 0x80>; |
| 118 | cell-index = <0>; |
| 119 | interrupt-parent = <&mpic>; |
| 120 | interrupts = <20 2>; |
| 121 | }; |
| 122 | dma-channel@80 { |
| 123 | compatible = "fsl,mpc8541-dma-channel", |
| 124 | "fsl,eloplus-dma-channel"; |
| 125 | reg = <0x80 0x80>; |
| 126 | cell-index = <1>; |
| 127 | interrupt-parent = <&mpic>; |
| 128 | interrupts = <21 2>; |
| 129 | }; |
| 130 | dma-channel@100 { |
| 131 | compatible = "fsl,mpc8541-dma-channel", |
| 132 | "fsl,eloplus-dma-channel"; |
| 133 | reg = <0x100 0x80>; |
| 134 | cell-index = <2>; |
| 135 | interrupt-parent = <&mpic>; |
| 136 | interrupts = <22 2>; |
| 137 | }; |
| 138 | dma-channel@180 { |
| 139 | compatible = "fsl,mpc8541-dma-channel", |
| 140 | "fsl,eloplus-dma-channel"; |
| 141 | reg = <0x180 0x80>; |
| 142 | cell-index = <3>; |
| 143 | interrupt-parent = <&mpic>; |
| 144 | interrupts = <23 2>; |
| 145 | }; |
| 146 | }; |
| 147 | |
| 148 | enet0: ethernet@24000 { |
| 149 | #address-cells = <1>; |
| 150 | #size-cells = <1>; |
| 151 | cell-index = <0>; |
| 152 | device_type = "network"; |
| 153 | model = "TSEC"; |
| 154 | compatible = "gianfar"; |
| 155 | reg = <0x24000 0x1000>; |
| 156 | ranges = <0x0 0x24000 0x1000>; |
| 157 | local-mac-address = [ 00 00 00 00 00 00 ]; |
| 158 | interrupts = <29 2 30 2 34 2>; |
| 159 | interrupt-parent = <&mpic>; |
| 160 | tbi-handle = <&tbi0>; |
| 161 | phy-handle = <&phy2>; |
| 162 | |
| 163 | mdio@520 { |
| 164 | #address-cells = <1>; |
| 165 | #size-cells = <0>; |
| 166 | compatible = "fsl,gianfar-mdio"; |
| 167 | reg = <0x520 0x20>; |
| 168 | |
| 169 | phy1: ethernet-phy@1 { |
| 170 | interrupt-parent = <&mpic>; |
| 171 | interrupts = <8 1>; |
| 172 | reg = <1>; |
| 173 | }; |
| 174 | phy2: ethernet-phy@2 { |
| 175 | interrupt-parent = <&mpic>; |
| 176 | interrupts = <8 1>; |
| 177 | reg = <2>; |
| 178 | }; |
| 179 | phy3: ethernet-phy@3 { |
| 180 | interrupt-parent = <&mpic>; |
| 181 | interrupts = <8 1>; |
| 182 | reg = <3>; |
| 183 | }; |
| 184 | tbi0: tbi-phy@11 { |
| 185 | reg = <0x11>; |
| 186 | device_type = "tbi-phy"; |
| 187 | }; |
| 188 | }; |
| 189 | }; |
| 190 | |
| 191 | enet1: ethernet@25000 { |
| 192 | #address-cells = <1>; |
| 193 | #size-cells = <1>; |
| 194 | cell-index = <1>; |
| 195 | device_type = "network"; |
| 196 | model = "TSEC"; |
| 197 | compatible = "gianfar"; |
| 198 | reg = <0x25000 0x1000>; |
| 199 | ranges = <0x0 0x25000 0x1000>; |
| 200 | local-mac-address = [ 00 00 00 00 00 00 ]; |
| 201 | interrupts = <35 2 36 2 40 2>; |
| 202 | interrupt-parent = <&mpic>; |
| 203 | tbi-handle = <&tbi1>; |
| 204 | phy-handle = <&phy1>; |
| 205 | |
| 206 | mdio@520 { |
| 207 | #address-cells = <1>; |
| 208 | #size-cells = <0>; |
| 209 | compatible = "fsl,gianfar-tbi"; |
| 210 | reg = <0x520 0x20>; |
| 211 | |
| 212 | tbi1: tbi-phy@11 { |
| 213 | reg = <0x11>; |
| 214 | device_type = "tbi-phy"; |
| 215 | }; |
| 216 | }; |
| 217 | }; |
| 218 | |
| 219 | serial0: serial@4500 { |
| 220 | cell-index = <0>; |
| 221 | device_type = "serial"; |
| 222 | compatible = "fsl,ns16550", "ns16550"; |
| 223 | reg = <0x4500 0x100>; // reg base, size |
| 224 | clock-frequency = <0>; // should we fill in in uboot? |
| 225 | interrupts = <42 2>; |
| 226 | interrupt-parent = <&mpic>; |
| 227 | }; |
| 228 | |
| 229 | serial1: serial@4600 { |
| 230 | cell-index = <1>; |
| 231 | device_type = "serial"; |
| 232 | compatible = "fsl,ns16550", "ns16550"; |
| 233 | reg = <0x4600 0x100>; // reg base, size |
| 234 | clock-frequency = <0>; // should we fill in in uboot? |
| 235 | interrupts = <42 2>; |
| 236 | interrupt-parent = <&mpic>; |
| 237 | }; |
| 238 | |
| 239 | crypto@30000 { |
| 240 | compatible = "fsl,sec2.0"; |
| 241 | reg = <0x30000 0x10000>; |
| 242 | interrupts = <45 2>; |
| 243 | interrupt-parent = <&mpic>; |
| 244 | fsl,num-channels = <4>; |
| 245 | fsl,channel-fifo-len = <24>; |
| 246 | fsl,exec-units-mask = <0x7e>; |
| 247 | fsl,descriptor-types-mask = <0x01010ebf>; |
| 248 | }; |
| 249 | |
| 250 | mpic: pic@40000 { |
| 251 | interrupt-controller; |
| 252 | #address-cells = <0>; |
| 253 | #interrupt-cells = <2>; |
| 254 | reg = <0x40000 0x40000>; |
| 255 | device_type = "open-pic"; |
| 256 | compatible = "chrp,open-pic"; |
| 257 | }; |
| 258 | |
| 259 | cpm@919c0 { |
| 260 | #address-cells = <1>; |
| 261 | #size-cells = <1>; |
| 262 | compatible = "fsl,mpc8541-cpm", "fsl,cpm2", "simple-bus"; |
| 263 | reg = <0x919c0 0x30>; |
| 264 | ranges; |
| 265 | |
| 266 | muram@80000 { |
| 267 | #address-cells = <1>; |
| 268 | #size-cells = <1>; |
| 269 | ranges = <0 0x80000 0x10000>; |
| 270 | |
| 271 | data@0 { |
| 272 | compatible = "fsl,cpm-muram-data"; |
| 273 | reg = <0 0x2000 0x9000 0x1000>; |
| 274 | }; |
| 275 | }; |
| 276 | |
| 277 | brg@919f0 { |
| 278 | compatible = "fsl,mpc8541-brg", |
| 279 | "fsl,cpm2-brg", |
| 280 | "fsl,cpm-brg"; |
| 281 | reg = <0x919f0 0x10 0x915f0 0x10>; |
| 282 | clock-frequency = <0>; |
| 283 | }; |
| 284 | |
| 285 | cpmpic: pic@90c00 { |
| 286 | interrupt-controller; |
| 287 | #address-cells = <0>; |
| 288 | #interrupt-cells = <2>; |
| 289 | interrupts = <46 2>; |
| 290 | interrupt-parent = <&mpic>; |
| 291 | reg = <0x90c00 0x80>; |
| 292 | compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic"; |
| 293 | }; |
| 294 | }; |
| 295 | }; |
| 296 | |
| 297 | pci0: pci@e0008000 { |
| 298 | #interrupt-cells = <1>; |
| 299 | #size-cells = <2>; |
| 300 | #address-cells = <3>; |
| 301 | compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; |
| 302 | device_type = "pci"; |
| 303 | reg = <0xe0008000 0x1000>; |
| 304 | clock-frequency = <66666666>; |
| 305 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 306 | interrupt-map = < |
| 307 | /* IDSEL 28 */ |
| 308 | 0xe000 0 0 1 &mpic 2 1 |
| 309 | 0xe000 0 0 2 &mpic 3 1 |
| 310 | 0xe000 0 0 3 &mpic 6 1 |
| 311 | 0xe000 0 0 4 &mpic 5 1 |
| 312 | |
| 313 | /* IDSEL 11 */ |
| 314 | 0x5800 0 0 1 &mpic 6 1 |
| 315 | 0x5800 0 0 2 &mpic 5 1 |
| 316 | >; |
| 317 | |
| 318 | interrupt-parent = <&mpic>; |
| 319 | interrupts = <24 2>; |
| 320 | bus-range = <0 0>; |
| 321 | ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 |
| 322 | 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>; |
| 323 | }; |
| 324 | }; |