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git01.mediatek.com / filogic / uboot / b35aa4f7b4ddadb58b2c20e407a95f1480e618b9 / . / dts / upstream / src / powerpc / stxssa8555.dts
blob: 96add25c904ba6ae22ff8ccbe2a5ed2f37057d4d [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * MPC8555-based STx GP3 Device Tree Source
4 *
5 * Copyright 2006, 2008 Freescale Semiconductor Inc.
6 *
7 * Copyright 2010 Silicon Turnkey Express LLC.
8 */
9
10/dts-v1/;
11
12/include/ "fsl/e500v1_power_isa.dtsi"
13
14/ {
15 model = "stx,gp3";
16 compatible = "stx,gp3-8560", "stx,gp3";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 PowerPC,8555@0 {
33 device_type = "cpu";
34 reg = <0x0>;
35 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot
42 next-level-cache = <&L2>;
43 };
44 };
45
46 memory {
47 device_type = "memory";
48 reg = <0x00000000 0x10000000>;
49 };
50
51 soc8555@e0000000 {
52 #address-cells = <1>;
53 #size-cells = <1>;
54 device_type = "soc";
55 compatible = "simple-bus";
56 ranges = <0x0 0xe0000000 0x100000>;
57 bus-frequency = <0>;
58
59 ecm-law@0 {
60 compatible = "fsl,ecm-law";
61 reg = <0x0 0x1000>;
62 fsl,num-laws = <8>;
63 };
64
65 ecm@1000 {
66 compatible = "fsl,mpc8555-ecm", "fsl,ecm";
67 reg = <0x1000 0x1000>;
68 interrupts = <17 2>;
69 interrupt-parent = <&mpic>;
70 };
71
72 memory-controller@2000 {
73 compatible = "fsl,mpc8555-memory-controller";
74 reg = <0x2000 0x1000>;
75 interrupt-parent = <&mpic>;
76 interrupts = <18 2>;
77 };
78
79 L2: l2-cache-controller@20000 {
80 compatible = "fsl,mpc8555-l2-cache-controller";
81 reg = <0x20000 0x1000>;
82 cache-line-size = <32>; // 32 bytes
83 cache-size = <0x40000>; // L2, 256K
84 interrupt-parent = <&mpic>;
85 interrupts = <16 2>;
86 };
87
88 i2c@3000 {
89 #address-cells = <1>;
90 #size-cells = <0>;
91 cell-index = <0>;
92 compatible = "fsl-i2c";
93 reg = <0x3000 0x100>;
94 interrupts = <43 2>;
95 interrupt-parent = <&mpic>;
96 dfsrr;
97 };
98
99 dma@21300 {
100 #address-cells = <1>;
101 #size-cells = <1>;
102 compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
103 reg = <0x21300 0x4>;
104 ranges = <0x0 0x21100 0x200>;
105 cell-index = <0>;
106 dma-channel@0 {
107 compatible = "fsl,mpc8555-dma-channel",
108 "fsl,eloplus-dma-channel";
109 reg = <0x0 0x80>;
110 cell-index = <0>;
111 interrupt-parent = <&mpic>;
112 interrupts = <20 2>;
113 };
114 dma-channel@80 {
115 compatible = "fsl,mpc8555-dma-channel",
116 "fsl,eloplus-dma-channel";
117 reg = <0x80 0x80>;
118 cell-index = <1>;
119 interrupt-parent = <&mpic>;
120 interrupts = <21 2>;
121 };
122 dma-channel@100 {
123 compatible = "fsl,mpc8555-dma-channel",
124 "fsl,eloplus-dma-channel";
125 reg = <0x100 0x80>;
126 cell-index = <2>;
127 interrupt-parent = <&mpic>;
128 interrupts = <22 2>;
129 };
130 dma-channel@180 {
131 compatible = "fsl,mpc8555-dma-channel",
132 "fsl,eloplus-dma-channel";
133 reg = <0x180 0x80>;
134 cell-index = <3>;
135 interrupt-parent = <&mpic>;
136 interrupts = <23 2>;
137 };
138 };
139
140 enet0: ethernet@24000 {
141 #address-cells = <1>;
142 #size-cells = <1>;
143 cell-index = <0>;
144 device_type = "network";
145 model = "TSEC";
146 compatible = "gianfar";
147 reg = <0x24000 0x1000>;
148 ranges = <0x0 0x24000 0x1000>;
149 local-mac-address = [ 00 00 00 00 00 00 ];
150 interrupts = <29 2 30 2 34 2>;
151 interrupt-parent = <&mpic>;
152 tbi-handle = <&tbi0>;
153 phy-handle = <&phy0>;
154
155 mdio@520 {
156 #address-cells = <1>;
157 #size-cells = <0>;
158 compatible = "fsl,gianfar-mdio";
159 reg = <0x520 0x20>;
160
161 phy0: ethernet-phy@2 {
162 interrupt-parent = <&mpic>;
163 interrupts = <5 1>;
164 reg = <0x2>;
165 };
166 phy1: ethernet-phy@4 {
167 interrupt-parent = <&mpic>;
168 interrupts = <5 1>;
169 reg = <0x4>;
170 };
171 tbi0: tbi-phy@11 {
172 reg = <0x11>;
173 device_type = "tbi-phy";
174 };
175 };
176 };
177
178 enet1: ethernet@25000 {
179 #address-cells = <1>;
180 #size-cells = <1>;
181 cell-index = <1>;
182 device_type = "network";
183 model = "TSEC";
184 compatible = "gianfar";
185 reg = <0x25000 0x1000>;
186 ranges = <0x0 0x25000 0x1000>;
187 local-mac-address = [ 00 00 00 00 00 00 ];
188 interrupts = <35 2 36 2 40 2>;
189 interrupt-parent = <&mpic>;
190 tbi-handle = <&tbi1>;
191 phy-handle = <&phy1>;
192
193 mdio@520 {
194 #address-cells = <1>;
195 #size-cells = <0>;
196 compatible = "fsl,gianfar-tbi";
197 reg = <0x520 0x20>;
198
199 tbi1: tbi-phy@11 {
200 reg = <0x11>;
201 device_type = "tbi-phy";
202 };
203 };
204 };
205
206 serial0: serial@4500 {
207 cell-index = <0>;
208 device_type = "serial";
209 compatible = "fsl,ns16550", "ns16550";
210 reg = <0x4500 0x100>; // reg base, size
211 clock-frequency = <0>; // should we fill in in uboot?
212 interrupts = <42 2>;
213 interrupt-parent = <&mpic>;
214 };
215
216 serial1: serial@4600 {
217 cell-index = <1>;
218 device_type = "serial";
219 compatible = "fsl,ns16550", "ns16550";
220 reg = <0x4600 0x100>; // reg base, size
221 clock-frequency = <0>; // should we fill in in uboot?
222 interrupts = <42 2>;
223 interrupt-parent = <&mpic>;
224 };
225
226 crypto@30000 {
227 compatible = "fsl,sec2.0";
228 reg = <0x30000 0x10000>;
229 interrupts = <45 2>;
230 interrupt-parent = <&mpic>;
231 fsl,num-channels = <4>;
232 fsl,channel-fifo-len = <24>;
233 fsl,exec-units-mask = <0x7e>;
234 fsl,descriptor-types-mask = <0x01010ebf>;
235 };
236
237 mpic: pic@40000 {
238 interrupt-controller;
239 #address-cells = <0>;
240 #interrupt-cells = <2>;
241 reg = <0x40000 0x40000>;
242 compatible = "chrp,open-pic";
243 device_type = "open-pic";
244 };
245
246 cpm@919c0 {
247 #address-cells = <1>;
248 #size-cells = <1>;
249 compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
250 reg = <0x919c0 0x30>;
251 ranges;
252
253 muram@80000 {
254 #address-cells = <1>;
255 #size-cells = <1>;
256 ranges = <0x0 0x80000 0x10000>;
257
258 data@0 {
259 compatible = "fsl,cpm-muram-data";
260 reg = <0x0 0x2000 0x9000 0x1000>;
261 };
262 };
263
264 brg@919f0 {
265 compatible = "fsl,mpc8555-brg",
266 "fsl,cpm2-brg",
267 "fsl,cpm-brg";
268 reg = <0x919f0 0x10 0x915f0 0x10>;
269 };
270
271 cpmpic: pic@90c00 {
272 interrupt-controller;
273 #address-cells = <0>;
274 #interrupt-cells = <2>;
275 interrupts = <46 2>;
276 interrupt-parent = <&mpic>;
277 reg = <0x90c00 0x80>;
278 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
279 };
280 };
281 };
282
283 pci0: pci@e0008000 {
284 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
285 interrupt-map = <
286
287 /* IDSEL 0x10 */
288 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
289 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
290 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
291 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
292
293 /* IDSEL 0x11 */
294 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
295 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
296 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
297 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
298
299 /* IDSEL 0x12 (Slot 1) */
300 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
301 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
302 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
303 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
304
305 /* IDSEL 0x13 (Slot 2) */
306 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
307 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
308 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
309 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
310
311 /* IDSEL 0x14 (Slot 3) */
312 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
313 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
314 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
315 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
316
317 /* IDSEL 0x15 (Slot 4) */
318 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
319 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
320 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
321 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
322
323 /* Bus 1 (Tundra Bridge) */
324 /* IDSEL 0x12 (ISA bridge) */
325 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
326 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
327 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
328 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
329 interrupt-parent = <&mpic>;
330 interrupts = <24 2>;
331 bus-range = <0 0>;
332 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
333 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
334 clock-frequency = <66666666>;
335 #interrupt-cells = <1>;
336 #size-cells = <2>;
337 #address-cells = <3>;
338 reg = <0xe0008000 0x1000>;
339 compatible = "fsl,mpc8540-pci";
340 device_type = "pci";
341
342 i8259@19000 {
343 interrupt-controller;
344 device_type = "interrupt-controller";
345 reg = <0x19000 0x0 0x0 0x0 0x1>;
346 #address-cells = <0>;
347 #interrupt-cells = <2>;
348 compatible = "chrp,iic";
349 interrupts = <1>;
350 interrupt-parent = <&pci0>;
351 };
352 };
353
354 pci1: pci@e0009000 {
355 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
356 interrupt-map = <
357
358 /* IDSEL 0x15 */
359 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
360 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
361 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
362 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
363 interrupt-parent = <&mpic>;
364 interrupts = <25 2>;
365 bus-range = <0 0>;
366 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
367 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
368 clock-frequency = <66666666>;
369 #interrupt-cells = <1>;
370 #size-cells = <2>;
371 #address-cells = <3>;
372 reg = <0xe0009000 0x1000>;
373 compatible = "fsl,mpc8540-pci";
374 device_type = "pci";
375 };
376};