blob: 69a93a0722f07f5c45ec6d5f817eed79231463ab [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/usb/cdns,usb3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Cadence USBSS-DRD controller
8
9maintainers:
10 - Pawel Laszczak <pawell@cadence.com>
11
12properties:
13 compatible:
14 const: cdns,usb3
15
16 reg:
17 items:
18 - description: OTG controller registers
19 - description: XHCI Host controller registers
20 - description: DEVICE controller registers
21
22 reg-names:
23 items:
24 - const: otg
25 - const: xhci
26 - const: dev
27
28 interrupts:
29 minItems: 3
30 items:
31 - description: XHCI host controller interrupt
32 - description: Device controller interrupt
33 - description: OTG/DRD controller interrupt
34 - description: interrupt used to wake up core, e.g when usbcmd.rs is
35 cleared by xhci core, this interrupt is optional
36
37 interrupt-names:
38 minItems: 3
39 items:
40 - const: host
41 - const: peripheral
42 - const: otg
43 - const: wakeup
44
45 dr_mode:
46 enum: [host, otg, peripheral]
47
48 maximum-speed:
49 enum: [super-speed, high-speed, full-speed]
50
51 phys:
52 minItems: 1
53 maxItems: 2
54
55 phy-names:
56 minItems: 1
57 maxItems: 2
58 items:
59 anyOf:
60 - const: cdns3,usb2-phy
61 - const: cdns3,usb3-phy
62
63 cdns,on-chip-buff-size:
64 description:
65 size of memory intended as internal memory for endpoints
66 buffers expressed in KB
67 $ref: /schemas/types.yaml#/definitions/uint16
68
69 cdns,phyrst-a-enable:
70 description: Enable resetting of PHY if Rx fail is detected
71 type: boolean
72
73required:
74 - compatible
75 - reg
76 - reg-names
77 - interrupts
78 - interrupt-names
79
80additionalProperties: false
81
82examples:
83 - |
84 #include <dt-bindings/interrupt-controller/arm-gic.h>
85 bus {
86 #address-cells = <2>;
87 #size-cells = <2>;
88
89 usb@6000000 {
90 compatible = "cdns,usb3";
91 reg = <0x00 0x6000000 0x00 0x10000>,
92 <0x00 0x6010000 0x00 0x10000>,
93 <0x00 0x6020000 0x00 0x10000>;
94 reg-names = "otg", "xhci", "dev";
95 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
98 interrupt-names = "host", "peripheral", "otg";
99 maximum-speed = "super-speed";
100 dr_mode = "otg";
101 };
102 };