Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | Qualcomm APQ8064 SATA PHY Controller |
| 2 | ------------------------------------ |
| 3 | |
| 4 | SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers. |
| 5 | Each SATA PHY controller should have its own node. |
| 6 | |
| 7 | Required properties: |
| 8 | - compatible: compatible list, contains "qcom,apq8064-sata-phy". |
| 9 | - reg: offset and length of the SATA PHY register set; |
| 10 | - #phy-cells: must be zero |
| 11 | - clocks: a list of phandles and clock-specifier pairs, one for each entry in |
| 12 | clock-names. |
| 13 | - clock-names: must be "cfg" for phy config clock. |
| 14 | |
| 15 | Example: |
| 16 | sata_phy: sata-phy@1b400000 { |
| 17 | compatible = "qcom,apq8064-sata-phy"; |
| 18 | reg = <0x1b400000 0x200>; |
| 19 | |
| 20 | clocks = <&gcc SATA_PHY_CFG_CLK>; |
| 21 | clock-names = "cfg"; |
| 22 | |
| 23 | #phy-cells = <0>; |
| 24 | }; |