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Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP PHY controller (USB, SC8280XP)
8
9maintainers:
10 - Vinod Koul <vkoul@kernel.org>
11
12description:
13 The QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16properties:
17 compatible:
18 enum:
19 - qcom,ipq6018-qmp-usb3-phy
20 - qcom,ipq8074-qmp-usb3-phy
21 - qcom,ipq9574-qmp-usb3-phy
22 - qcom,msm8996-qmp-usb3-phy
23 - qcom,msm8998-qmp-usb3-phy
24 - qcom,qcm2290-qmp-usb3-phy
25 - qcom,sa8775p-qmp-usb3-uni-phy
26 - qcom,sc8280xp-qmp-usb3-uni-phy
27 - qcom,sdm845-qmp-usb3-uni-phy
28 - qcom,sdx55-qmp-usb3-uni-phy
29 - qcom,sdx65-qmp-usb3-uni-phy
30 - qcom,sdx75-qmp-usb3-uni-phy
31 - qcom,sm6115-qmp-usb3-phy
32 - qcom,sm8150-qmp-usb3-uni-phy
33 - qcom,sm8250-qmp-usb3-uni-phy
34 - qcom,sm8350-qmp-usb3-uni-phy
Tom Rini93743d22024-04-01 09:08:13 -040035 - qcom,x1e80100-qmp-usb3-uni-phy
Tom Rini53633a82024-02-29 12:33:36 -050036
37
38 reg:
39 maxItems: 1
40
41 clocks:
42 minItems: 4
43 maxItems: 5
44
45 clock-names:
46 minItems: 4
47 maxItems: 5
48
49 power-domains:
50 maxItems: 1
51
52 resets:
53 maxItems: 2
54
55 reset-names:
56 items:
57 - const: phy
58 - const: phy_phy
59
60 vdda-phy-supply: true
61
62 vdda-pll-supply: true
63
64 "#clock-cells":
65 const: 0
66
67 clock-output-names:
68 maxItems: 1
69
70 "#phy-cells":
71 const: 0
72
73required:
74 - compatible
75 - reg
76 - clocks
77 - clock-names
78 - resets
79 - reset-names
80 - vdda-phy-supply
81 - vdda-pll-supply
82 - "#clock-cells"
83 - clock-output-names
84 - "#phy-cells"
85
86allOf:
87 - if:
88 properties:
89 compatible:
90 contains:
91 enum:
92 - qcom,ipq6018-qmp-usb3-phy
93 - qcom,ipq8074-qmp-usb3-phy
94 - qcom,ipq9574-qmp-usb3-phy
95 - qcom,msm8996-qmp-usb3-phy
96 - qcom,msm8998-qmp-usb3-phy
97 - qcom,sdx55-qmp-usb3-uni-phy
98 - qcom,sdx65-qmp-usb3-uni-phy
99 - qcom,sdx75-qmp-usb3-uni-phy
100 then:
101 properties:
102 clocks:
103 maxItems: 4
104 clock-names:
105 items:
106 - const: aux
107 - const: ref
108 - const: cfg_ahb
109 - const: pipe
110
111 - if:
112 properties:
113 compatible:
114 contains:
115 enum:
116 - qcom,qcm2290-qmp-usb3-phy
117 - qcom,sm6115-qmp-usb3-phy
118 then:
119 properties:
120 clocks:
121 maxItems: 4
122 clock-names:
123 items:
124 - const: cfg_ahb
125 - const: ref
126 - const: com_aux
127 - const: pipe
128
129 - if:
130 properties:
131 compatible:
132 contains:
133 enum:
134 - qcom,sa8775p-qmp-usb3-uni-phy
135 - qcom,sc8280xp-qmp-usb3-uni-phy
136 - qcom,sm8150-qmp-usb3-uni-phy
137 - qcom,sm8250-qmp-usb3-uni-phy
138 - qcom,sm8350-qmp-usb3-uni-phy
Tom Rini93743d22024-04-01 09:08:13 -0400139 - qcom,x1e80100-qmp-usb3-uni-phy
Tom Rini53633a82024-02-29 12:33:36 -0500140 then:
141 properties:
142 clocks:
143 maxItems: 4
144 clock-names:
145 items:
146 - const: aux
147 - const: ref
148 - const: com_aux
149 - const: pipe
150
151 - if:
152 properties:
153 compatible:
154 contains:
155 enum:
156 - qcom,sdm845-qmp-usb3-uni-phy
157 then:
158 properties:
159 clocks:
160 maxItems: 5
161 clock-names:
162 items:
163 - const: aux
164 - const: cfg_ahb
165 - const: ref
166 - const: com_aux
167 - const: pipe
168
169 - if:
170 properties:
171 compatible:
172 contains:
173 enum:
174 - qcom,sa8775p-qmp-usb3-uni-phy
175 - qcom,sc8280xp-qmp-usb3-uni-phy
Tom Rini93743d22024-04-01 09:08:13 -0400176 - qcom,x1e80100-qmp-usb3-uni-phy
Tom Rini53633a82024-02-29 12:33:36 -0500177 then:
178 required:
179 - power-domains
180
181additionalProperties: false
182
183examples:
184 - |
185 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
186 #include <dt-bindings/clock/qcom,rpmh.h>
187
188 phy@88ef000 {
189 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
190 reg = <0x088ef000 0x2000>;
191
192 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
193 <&gcc GCC_USB3_MP0_CLKREF_CLK>,
194 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
195 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
196 clock-names = "aux", "ref", "com_aux", "pipe";
197
198 power-domains = <&gcc USB30_MP_GDSC>;
199
200 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
201 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
202 reset-names = "phy", "phy_phy";
203
204 vdda-phy-supply = <&vreg_l3a>;
205 vdda-pll-supply = <&vreg_l5a>;
206
207 #clock-cells = <0>;
208 clock-output-names = "usb2_phy0_pipe_clk";
209
210 #phy-cells = <0>;
211 };