| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | * Nios II Processor Binding |
| 2 | |
| 3 | This binding specifies what properties available in the device tree |
| 4 | representation of a Nios II Processor Core. |
| 5 | |
| 6 | Users can use sopc2dts tool for generating device tree sources (dts) from a |
| 7 | Qsys system. See more detail in: http://www.alterawiki.com/wiki/Sopc2dts |
| 8 | |
| 9 | Required properties: |
| 10 | |
| 11 | - compatible: Compatible property value should be "altr,nios2-1.0". |
| 12 | - reg: Contains CPU index. |
| 13 | - interrupt-controller: Specifies that the node is an interrupt controller |
| 14 | - #interrupt-cells: Specifies the number of cells needed to encode an |
| 15 | interrupt source, should be 1. |
| 16 | - clock-frequency: Contains the clock frequency for CPU, in Hz. |
| 17 | - dcache-line-size: Contains data cache line size. |
| 18 | - icache-line-size: Contains instruction line size. |
| 19 | - dcache-size: Contains data cache size. |
| 20 | - icache-size: Contains instruction cache size. |
| 21 | - altr,pid-num-bits: Specifies the number of bits to use to represent the process |
| 22 | identifier (PID). |
| 23 | - altr,tlb-num-ways: Specifies the number of set-associativity ways in the TLB. |
| 24 | - altr,tlb-num-entries: Specifies the number of entries in the TLB. |
| 25 | - altr,tlb-ptr-sz: Specifies size of TLB pointer. |
| 26 | - altr,has-mul: Specifies CPU hardware multiply support, should be 1. |
| 27 | - altr,has-mmu: Specifies CPU support MMU support, should be 1. |
| 28 | - altr,has-initda: Specifies CPU support initda instruction, should be 1. |
| 29 | - altr,reset-addr: Specifies CPU reset address |
| 30 | - altr,fast-tlb-miss-addr: Specifies CPU fast TLB miss exception address |
| 31 | - altr,exception-addr: Specifies CPU exception address |
| 32 | |
| 33 | Optional properties: |
| 34 | - altr,has-div: Specifies CPU hardware divide support |
| 35 | - altr,implementation: Nios II core implementation, this should be "fast"; |
| 36 | |
| 37 | Example: |
| 38 | |
| 39 | cpu@0 { |
| 40 | device_type = "cpu"; |
| 41 | compatible = "altr,nios2-1.0"; |
| 42 | reg = <0>; |
| 43 | interrupt-controller; |
| 44 | #interrupt-cells = <1>; |
| 45 | clock-frequency = <125000000>; |
| 46 | dcache-line-size = <32>; |
| 47 | icache-line-size = <32>; |
| 48 | dcache-size = <32768>; |
| 49 | icache-size = <32768>; |
| 50 | altr,implementation = "fast"; |
| 51 | altr,pid-num-bits = <8>; |
| 52 | altr,tlb-num-ways = <16>; |
| 53 | altr,tlb-num-entries = <128>; |
| 54 | altr,tlb-ptr-sz = <7>; |
| 55 | altr,has-div = <1>; |
| 56 | altr,has-mul = <1>; |
| 57 | altr,reset-addr = <0xc2800000>; |
| 58 | altr,fast-tlb-miss-addr = <0xc7fff400>; |
| 59 | altr,exception-addr = <0xd0000020>; |
| 60 | altr,has-initda = <1>; |
| 61 | altr,has-mmu = <1>; |
| 62 | }; |