blob: 42804d95529342e463ab98c2665d2f019c9bc77d [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/snps,dwcmshc-sdhci.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys Designware Mobile Storage Host Controller
8
9maintainers:
10 - Ulf Hansson <ulf.hansson@linaro.org>
11 - Jisheng Zhang <Jisheng.Zhang@synaptics.com>
12
13allOf:
14 - $ref: mmc-controller.yaml#
15
16properties:
17 compatible:
18 enum:
19 - rockchip,rk3568-dwcmshc
20 - rockchip,rk3588-dwcmshc
21 - snps,dwcmshc-sdhci
Tom Rini93743d22024-04-01 09:08:13 -040022 - thead,th1520-dwcmshc
Tom Rini53633a82024-02-29 12:33:36 -050023
24 reg:
25 maxItems: 1
26
27 interrupts:
28 maxItems: 1
29
30 clocks:
31 minItems: 1
32 items:
33 - description: core clock
34 - description: bus clock for optional
35 - description: axi clock for rockchip specified
36 - description: block clock for rockchip specified
37 - description: timer clock for rockchip specified
38
39
40 clock-names:
41 minItems: 1
42 items:
43 - const: core
44 - const: bus
45 - const: axi
46 - const: block
47 - const: timer
48
49 resets:
50 maxItems: 5
51
52 reset-names:
53 items:
54 - const: core
55 - const: bus
56 - const: axi
57 - const: block
58 - const: timer
59
60 rockchip,txclk-tapnum:
61 description: Specify the number of delay for tx sampling.
62 $ref: /schemas/types.yaml#/definitions/uint8
63
64
65required:
66 - compatible
67 - reg
68 - interrupts
69 - clocks
70 - clock-names
71
72unevaluatedProperties: false
73
74examples:
75 - |
76 mmc@fe310000 {
77 compatible = "rockchip,rk3568-dwcmshc";
78 reg = <0xfe310000 0x10000>;
79 interrupts = <0 25 0x4>;
80 clocks = <&cru 17>, <&cru 18>, <&cru 19>, <&cru 20>, <&cru 21>;
81 clock-names = "core", "bus", "axi", "block", "timer";
82 bus-width = <8>;
83 #address-cells = <1>;
84 #size-cells = <0>;
85 };
86 - |
87 mmc@aa0000 {
88 compatible = "snps,dwcmshc-sdhci";
89 reg = <0xaa000 0x1000>;
90 interrupts = <0 25 0x4>;
91 clocks = <&cru 17>, <&cru 18>;
92 clock-names = "core", "bus";
93 bus-width = <8>;
94 #address-cells = <1>;
95 #size-cells = <0>;
96 };
97
98...