Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/media/i2c/toshiba,tc358746.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Toshiba TC358746 Parallel to MIPI CSI2 Bridge |
| 8 | |
| 9 | maintainers: |
| 10 | - Marco Felsch <kernel@pengutronix.de> |
| 11 | |
| 12 | description: |- |
| 13 | The Toshiba TC358746 converts a parallel video stream into a MIPI CSI-2 |
| 14 | stream. The direction can be either parallel-in -> csi-out or csi-in -> |
| 15 | parallel-out The chip is programmable through I2C and SPI but the SPI |
| 16 | interface is only supported in parallel-in -> csi-out mode. |
| 17 | |
| 18 | Note that the current device tree bindings only support the |
| 19 | parallel-in -> csi-out path. |
| 20 | |
| 21 | properties: |
| 22 | compatible: |
| 23 | const: toshiba,tc358746 |
| 24 | |
| 25 | reg: |
| 26 | maxItems: 1 |
| 27 | |
| 28 | clocks: |
| 29 | description: |
| 30 | The phandle to the reference clock source. This corresponds to the |
| 31 | hardware pin REFCLK. |
| 32 | maxItems: 1 |
| 33 | |
| 34 | clock-names: |
| 35 | const: refclk |
| 36 | |
| 37 | "#clock-cells": |
| 38 | description: | |
| 39 | The bridge can act as clock provider for the sensor. To enable this |
| 40 | support #clock-cells must be specified. Attention if this feature is used |
| 41 | then the mclk rate must be at least: (2 * link-frequency) / 8 |
| 42 | `------------------ยด ^ |
| 43 | internal PLL rate smallest possible |
| 44 | mclk-div |
| 45 | const: 0 |
| 46 | |
| 47 | clock-output-names: |
| 48 | description: |
| 49 | The clock name of the MCLK output, the default name is tc358746-mclk. |
| 50 | maxItems: 1 |
| 51 | |
| 52 | vddc-supply: |
| 53 | description: Digital core voltage supply, 1.2 volts |
| 54 | |
| 55 | vddio-supply: |
| 56 | description: Digital I/O voltage supply, 1.8 volts |
| 57 | |
| 58 | vddmipi-supply: |
| 59 | description: MIPI CSI phy voltage supply, 1.2 volts |
| 60 | |
| 61 | reset-gpios: |
| 62 | description: |
| 63 | The phandle and specifier for the GPIO that controls the chip reset. |
| 64 | This corresponds to the hardware pin RESX which is physically active low. |
| 65 | maxItems: 1 |
| 66 | |
| 67 | ports: |
| 68 | $ref: /schemas/graph.yaml#/properties/ports |
| 69 | properties: |
| 70 | port@0: |
| 71 | $ref: /schemas/graph.yaml#/$defs/port-base |
| 72 | unevaluatedProperties: false |
| 73 | description: Input port |
| 74 | |
| 75 | properties: |
| 76 | endpoint: |
| 77 | $ref: /schemas/media/video-interfaces.yaml# |
| 78 | unevaluatedProperties: false |
| 79 | |
| 80 | properties: |
| 81 | hsync-active: true |
| 82 | vsync-active: true |
| 83 | bus-type: |
| 84 | enum: [ 5, 6 ] |
| 85 | |
| 86 | required: |
| 87 | - hsync-active |
| 88 | - vsync-active |
| 89 | - bus-type |
| 90 | |
| 91 | port@1: |
| 92 | $ref: /schemas/graph.yaml#/$defs/port-base |
| 93 | unevaluatedProperties: false |
| 94 | description: Output port |
| 95 | |
| 96 | properties: |
| 97 | endpoint: |
| 98 | $ref: /schemas/media/video-interfaces.yaml# |
| 99 | unevaluatedProperties: false |
| 100 | |
| 101 | properties: |
| 102 | data-lanes: |
| 103 | minItems: 1 |
| 104 | maxItems: 4 |
| 105 | |
| 106 | clock-noncontinuous: true |
| 107 | link-frequencies: true |
| 108 | |
| 109 | required: |
| 110 | - data-lanes |
| 111 | - link-frequencies |
| 112 | |
| 113 | required: |
| 114 | - port@0 |
| 115 | - port@1 |
| 116 | |
| 117 | required: |
| 118 | - compatible |
| 119 | - reg |
| 120 | - clocks |
| 121 | - clock-names |
| 122 | - vddc-supply |
| 123 | - vddio-supply |
| 124 | - vddmipi-supply |
| 125 | - ports |
| 126 | |
| 127 | additionalProperties: false |
| 128 | |
| 129 | examples: |
| 130 | - | |
| 131 | #include <dt-bindings/gpio/gpio.h> |
| 132 | |
| 133 | i2c { |
| 134 | #address-cells = <1>; |
| 135 | #size-cells = <0>; |
| 136 | |
| 137 | csi-bridge@e { |
| 138 | compatible = "toshiba,tc358746"; |
| 139 | reg = <0xe>; |
| 140 | |
| 141 | clocks = <&refclk>; |
| 142 | clock-names = "refclk"; |
| 143 | |
| 144 | reset-gpios = <&gpio 2 GPIO_ACTIVE_LOW>; |
| 145 | |
| 146 | vddc-supply = <&v1_2d>; |
| 147 | vddio-supply = <&v1_8d>; |
| 148 | vddmipi-supply = <&v1_2d>; |
| 149 | |
| 150 | /* sensor mclk provider */ |
| 151 | #clock-cells = <0>; |
| 152 | |
| 153 | ports { |
| 154 | #address-cells = <1>; |
| 155 | #size-cells = <0>; |
| 156 | |
| 157 | /* Input */ |
| 158 | port@0 { |
| 159 | reg = <0>; |
| 160 | tc358746_in: endpoint { |
| 161 | remote-endpoint = <&sensor_out>; |
| 162 | hsync-active = <0>; |
| 163 | vsync-active = <0>; |
| 164 | bus-type = <5>; |
| 165 | }; |
| 166 | }; |
| 167 | |
| 168 | /* Output */ |
| 169 | port@1 { |
| 170 | reg = <1>; |
| 171 | tc358746_out: endpoint { |
| 172 | remote-endpoint = <&mipi_csi2_in>; |
| 173 | data-lanes = <1 2>; |
| 174 | clock-noncontinuous; |
| 175 | link-frequencies = /bits/ 64 <216000000>; |
| 176 | }; |
| 177 | }; |
| 178 | }; |
| 179 | }; |
| 180 | }; |