Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/gpio/gpio-davinci.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: GPIO controller for Davinci and keystone devices |
| 8 | |
| 9 | maintainers: |
| 10 | - Keerthy <j-keerthy@ti.com> |
| 11 | |
| 12 | properties: |
| 13 | compatible: |
| 14 | oneOf: |
| 15 | - items: |
| 16 | - enum: |
| 17 | - ti,k2g-gpio |
| 18 | - ti,am654-gpio |
| 19 | - ti,j721e-gpio |
| 20 | - ti,am64-gpio |
| 21 | - const: ti,keystone-gpio |
| 22 | |
| 23 | - items: |
| 24 | - enum: |
| 25 | - ti,dm6441-gpio |
| 26 | - ti,keystone-gpio |
| 27 | |
| 28 | reg: |
| 29 | maxItems: 1 |
| 30 | |
| 31 | gpio-controller: true |
| 32 | |
| 33 | gpio-ranges: true |
| 34 | |
| 35 | gpio-line-names: |
| 36 | description: strings describing the names of each gpio line. |
| 37 | minItems: 1 |
| 38 | maxItems: 144 |
| 39 | |
| 40 | "#gpio-cells": |
| 41 | const: 2 |
| 42 | description: |
| 43 | first cell is the pin number and second cell is used to specify optional parameters (unused). |
| 44 | |
| 45 | interrupts: |
| 46 | description: |
| 47 | The interrupts are specified as per the interrupt parent. Only banked |
| 48 | or unbanked IRQs are supported at a time. If the interrupts are |
| 49 | banked then provide list of interrupts corresponding to each bank, else |
| 50 | provide the list of interrupts for each gpio. |
| 51 | minItems: 1 |
| 52 | maxItems: 100 |
| 53 | |
| 54 | ti,ngpio: |
| 55 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 56 | description: The number of GPIO pins supported consecutively. |
| 57 | minimum: 1 |
| 58 | |
| 59 | ti,davinci-gpio-unbanked: |
| 60 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 61 | description: The number of GPIOs that have an individual interrupt line to processor. |
| 62 | minimum: 0 |
| 63 | |
| 64 | clocks: |
| 65 | maxItems: 1 |
| 66 | |
| 67 | clock-names: |
| 68 | const: gpio |
| 69 | |
| 70 | interrupt-controller: true |
| 71 | |
| 72 | power-domains: |
| 73 | maxItems: 1 |
| 74 | |
| 75 | "#interrupt-cells": |
| 76 | const: 2 |
| 77 | |
| 78 | patternProperties: |
| 79 | "^(.+-hog(-[0-9]+)?)$": |
| 80 | type: object |
| 81 | |
| 82 | required: |
| 83 | - gpio-hog |
| 84 | |
| 85 | required: |
| 86 | - compatible |
| 87 | - reg |
| 88 | - gpio-controller |
| 89 | - "#gpio-cells" |
| 90 | - interrupts |
| 91 | - ti,ngpio |
| 92 | - ti,davinci-gpio-unbanked |
| 93 | - clocks |
| 94 | - clock-names |
| 95 | |
| 96 | additionalProperties: false |
| 97 | |
| 98 | examples: |
| 99 | - | |
| 100 | #include<dt-bindings/interrupt-controller/arm-gic.h> |
| 101 | |
| 102 | gpio0: gpio@2603000 { |
| 103 | compatible = "ti,k2g-gpio", "ti,keystone-gpio"; |
| 104 | reg = <0x02603000 0x100>; |
| 105 | gpio-controller; |
| 106 | #gpio-cells = <2>; |
| 107 | interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>, |
| 108 | <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>, |
| 109 | <GIC_SPI 434 IRQ_TYPE_EDGE_RISING>, |
| 110 | <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>, |
| 111 | <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>, |
| 112 | <GIC_SPI 437 IRQ_TYPE_EDGE_RISING>, |
| 113 | <GIC_SPI 438 IRQ_TYPE_EDGE_RISING>, |
| 114 | <GIC_SPI 439 IRQ_TYPE_EDGE_RISING>, |
| 115 | <GIC_SPI 440 IRQ_TYPE_EDGE_RISING>; |
| 116 | interrupt-controller; |
| 117 | #interrupt-cells = <2>; |
| 118 | ti,ngpio = <144>; |
| 119 | ti,davinci-gpio-unbanked = <0>; |
| 120 | clocks = <&k2g_clks 0x001b 0x0>; |
| 121 | clock-names = "gpio"; |
| 122 | }; |
| 123 | |
| 124 | - | |
| 125 | #include<dt-bindings/interrupt-controller/arm-gic.h> |
| 126 | |
| 127 | gpio1: gpio@260bf00 { |
| 128 | compatible = "ti,keystone-gpio"; |
| 129 | reg = <0x0260bf00 0x100>; |
| 130 | gpio-controller; |
| 131 | #gpio-cells = <2>; |
| 132 | /* HW Interrupts mapped to GPIO pins */ |
| 133 | interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>, |
| 134 | <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>, |
| 135 | <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, |
| 136 | <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>, |
| 137 | <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, |
| 138 | <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, |
| 139 | <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, |
| 140 | <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, |
| 141 | <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, |
| 142 | <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, |
| 143 | <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, |
| 144 | <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, |
| 145 | <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, |
| 146 | <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, |
| 147 | <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, |
| 148 | <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, |
| 149 | <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, |
| 150 | <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, |
| 151 | <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, |
| 152 | <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, |
| 153 | <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>, |
| 154 | <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, |
| 155 | <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>, |
| 156 | <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>, |
| 157 | <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>, |
| 158 | <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, |
| 159 | <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>, |
| 160 | <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>, |
| 161 | <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>, |
| 162 | <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, |
| 163 | <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>, |
| 164 | <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; |
| 165 | clocks = <&clkgpio>; |
| 166 | clock-names = "gpio"; |
| 167 | ti,ngpio = <32>; |
| 168 | ti,davinci-gpio-unbanked = <32>; |
| 169 | }; |
| 170 | |
| 171 | - | |
| 172 | wkup_gpio0: gpio0@42110000 { |
| 173 | compatible = "ti,am654-gpio", "ti,keystone-gpio"; |
| 174 | reg = <0x42110000 0x100>; |
| 175 | gpio-controller; |
| 176 | #gpio-cells = <2>; |
| 177 | interrupt-parent = <&intr_wkup_gpio>; |
| 178 | interrupts = <60>, <61>, <62>, <63>; |
| 179 | interrupt-controller; |
| 180 | #interrupt-cells = <2>; |
| 181 | ti,ngpio = <56>; |
| 182 | ti,davinci-gpio-unbanked = <0>; |
| 183 | clocks = <&k3_clks 59 0>; |
| 184 | clock-names = "gpio"; |
| 185 | }; |