| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/cache/qcom,llcc.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Last Level Cache Controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Bjorn Andersson <andersson@kernel.org> |
| 11 | |
| 12 | description: | |
| 13 | LLCC (Last Level Cache Controller) provides last level of cache memory in SoC, |
| 14 | that can be shared by multiple clients. Clients here are different cores in the |
| 15 | SoC, the idea is to minimize the local caches at the clients and migrate to |
| 16 | common pool of memory. Cache memory is divided into partitions called slices |
| 17 | which are assigned to clients. Clients can query the slice details, activate |
| 18 | and deactivate them. |
| 19 | |
| 20 | properties: |
| 21 | compatible: |
| 22 | enum: |
| 23 | - qcom,qdu1000-llcc |
| 24 | - qcom,sc7180-llcc |
| 25 | - qcom,sc7280-llcc |
| 26 | - qcom,sc8180x-llcc |
| 27 | - qcom,sc8280xp-llcc |
| 28 | - qcom,sdm845-llcc |
| 29 | - qcom,sm6350-llcc |
| 30 | - qcom,sm7150-llcc |
| 31 | - qcom,sm8150-llcc |
| 32 | - qcom,sm8250-llcc |
| 33 | - qcom,sm8350-llcc |
| 34 | - qcom,sm8450-llcc |
| 35 | - qcom,sm8550-llcc |
| Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame] | 36 | - qcom,sm8650-llcc |
| 37 | - qcom,x1e80100-llcc |
| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 38 | |
| 39 | reg: |
| 40 | minItems: 2 |
| 41 | maxItems: 9 |
| 42 | |
| 43 | reg-names: |
| 44 | minItems: 2 |
| 45 | maxItems: 9 |
| 46 | |
| 47 | interrupts: |
| 48 | maxItems: 1 |
| 49 | |
| 50 | nvmem-cells: |
| 51 | items: |
| 52 | - description: Reference to an nvmem node for multi channel DDR |
| 53 | |
| 54 | nvmem-cell-names: |
| 55 | items: |
| 56 | - const: multi-chan-ddr |
| 57 | |
| 58 | required: |
| 59 | - compatible |
| 60 | - reg |
| 61 | - reg-names |
| 62 | |
| 63 | allOf: |
| 64 | - if: |
| 65 | properties: |
| 66 | compatible: |
| 67 | contains: |
| 68 | enum: |
| Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame] | 69 | - qcom,qdu1000-llcc |
| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 70 | - qcom,sc7180-llcc |
| 71 | - qcom,sm6350-llcc |
| 72 | then: |
| 73 | properties: |
| 74 | reg: |
| 75 | items: |
| 76 | - description: LLCC0 base register region |
| 77 | - description: LLCC broadcast base register region |
| 78 | reg-names: |
| 79 | items: |
| 80 | - const: llcc0_base |
| 81 | - const: llcc_broadcast_base |
| 82 | |
| 83 | - if: |
| 84 | properties: |
| 85 | compatible: |
| 86 | contains: |
| 87 | enum: |
| 88 | - qcom,sc7280-llcc |
| 89 | then: |
| 90 | properties: |
| 91 | reg: |
| 92 | items: |
| 93 | - description: LLCC0 base register region |
| 94 | - description: LLCC1 base register region |
| 95 | - description: LLCC broadcast base register region |
| 96 | reg-names: |
| 97 | items: |
| 98 | - const: llcc0_base |
| 99 | - const: llcc1_base |
| 100 | - const: llcc_broadcast_base |
| 101 | |
| 102 | - if: |
| 103 | properties: |
| 104 | compatible: |
| 105 | contains: |
| 106 | enum: |
| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 107 | - qcom,sc8180x-llcc |
| 108 | - qcom,sc8280xp-llcc |
| Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame] | 109 | - qcom,x1e80100-llcc |
| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 110 | then: |
| 111 | properties: |
| 112 | reg: |
| 113 | items: |
| 114 | - description: LLCC0 base register region |
| 115 | - description: LLCC1 base register region |
| 116 | - description: LLCC2 base register region |
| 117 | - description: LLCC3 base register region |
| 118 | - description: LLCC4 base register region |
| 119 | - description: LLCC5 base register region |
| 120 | - description: LLCC6 base register region |
| 121 | - description: LLCC7 base register region |
| 122 | - description: LLCC broadcast base register region |
| 123 | reg-names: |
| 124 | items: |
| 125 | - const: llcc0_base |
| 126 | - const: llcc1_base |
| 127 | - const: llcc2_base |
| 128 | - const: llcc3_base |
| 129 | - const: llcc4_base |
| 130 | - const: llcc5_base |
| 131 | - const: llcc6_base |
| 132 | - const: llcc7_base |
| 133 | - const: llcc_broadcast_base |
| 134 | |
| 135 | - if: |
| 136 | properties: |
| 137 | compatible: |
| 138 | contains: |
| 139 | enum: |
| 140 | - qcom,sdm845-llcc |
| 141 | - qcom,sm8150-llcc |
| 142 | - qcom,sm8250-llcc |
| 143 | - qcom,sm8350-llcc |
| 144 | - qcom,sm8450-llcc |
| 145 | - qcom,sm8550-llcc |
| 146 | then: |
| 147 | properties: |
| 148 | reg: |
| 149 | items: |
| 150 | - description: LLCC0 base register region |
| 151 | - description: LLCC1 base register region |
| 152 | - description: LLCC2 base register region |
| 153 | - description: LLCC3 base register region |
| 154 | - description: LLCC broadcast base register region |
| 155 | reg-names: |
| 156 | items: |
| 157 | - const: llcc0_base |
| 158 | - const: llcc1_base |
| 159 | - const: llcc2_base |
| 160 | - const: llcc3_base |
| 161 | - const: llcc_broadcast_base |
| 162 | |
| 163 | additionalProperties: false |
| 164 | |
| 165 | examples: |
| 166 | - | |
| 167 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 168 | |
| 169 | soc { |
| 170 | #address-cells = <2>; |
| 171 | #size-cells = <2>; |
| 172 | |
| 173 | system-cache-controller@1100000 { |
| 174 | compatible = "qcom,sdm845-llcc"; |
| 175 | reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>, |
| 176 | <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, |
| 177 | <0 0x01300000 0 0x50000>; |
| 178 | reg-names = "llcc0_base", "llcc1_base", "llcc2_base", |
| 179 | "llcc3_base", "llcc_broadcast_base"; |
| 180 | interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; |
| 181 | }; |
| 182 | }; |