| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
| 2 | # Copyright 2021, Arm Ltd |
| 3 | %YAML 1.2 |
| 4 | --- |
| 5 | $id: http://devicetree.org/schemas/arm/arm,trace-buffer-extension.yaml# |
| 6 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 7 | |
| 8 | title: ARM Trace Buffer Extensions |
| 9 | |
| 10 | maintainers: |
| 11 | - Anshuman Khandual <anshuman.khandual@arm.com> |
| 12 | |
| 13 | description: | |
| 14 | Arm Trace Buffer Extension (TRBE) is a per CPU component |
| 15 | for storing trace generated on the CPU to memory. It is |
| 16 | accessed via CPU system registers. The software can verify |
| 17 | if it is permitted to use the component by checking the |
| 18 | TRBIDR register. |
| 19 | |
| 20 | properties: |
| 21 | $nodename: |
| 22 | const: trbe |
| 23 | |
| 24 | compatible: |
| 25 | items: |
| 26 | - const: arm,trace-buffer-extension |
| 27 | |
| 28 | interrupts: |
| 29 | description: | |
| 30 | Exactly 1 PPI must be listed. For heterogeneous systems where |
| 31 | TRBE is only supported on a subset of the CPUs, please consult |
| 32 | the arm,gic-v3 binding for details on describing a PPI partition. |
| 33 | maxItems: 1 |
| 34 | |
| 35 | required: |
| 36 | - compatible |
| 37 | - interrupts |
| 38 | |
| 39 | additionalProperties: false |
| 40 | |
| 41 | examples: |
| 42 | |
| 43 | - | |
| 44 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 45 | |
| 46 | trbe { |
| 47 | compatible = "arm,trace-buffer-extension"; |
| 48 | interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| 49 | }; |
| 50 | ... |