Dirk Eibach | b355f17 | 2015-10-28 11:46:32 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * (C) Copyright 2014 |
| 3 | * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | /* Chrontel CH7301C DVI Transmitter */ |
| 9 | |
| 10 | #include <common.h> |
| 11 | #include <asm/io.h> |
| 12 | #include <errno.h> |
| 13 | #include <i2c.h> |
| 14 | |
| 15 | #define CH7301_I2C_ADDR 0x75 |
| 16 | |
| 17 | enum { |
| 18 | CH7301_CM = 0x1c, /* Clock Mode Register */ |
| 19 | CH7301_IC = 0x1d, /* Input Clock Register */ |
| 20 | CH7301_GPIO = 0x1e, /* GPIO Control Register */ |
| 21 | CH7301_IDF = 0x1f, /* Input Data Format Register */ |
| 22 | CH7301_CD = 0x20, /* Connection Detect Register */ |
| 23 | CH7301_DC = 0x21, /* DAC Control Register */ |
| 24 | CH7301_HPD = 0x23, /* Hot Plug Detection Register */ |
| 25 | CH7301_TCTL = 0x31, /* DVI Control Input Register */ |
| 26 | CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */ |
| 27 | CH7301_TPD = 0x34, /* DVI PLL Divide Register */ |
| 28 | CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */ |
| 29 | CH7301_TPF = 0x36, /* DVI PLL Filter Register */ |
| 30 | CH7301_TCT = 0x37, /* DVI Clock Test Register */ |
| 31 | CH7301_TSTP = 0x48, /* Test Pattern Register */ |
| 32 | CH7301_PM = 0x49, /* Power Management register */ |
| 33 | CH7301_VID = 0x4a, /* Version ID Register */ |
| 34 | CH7301_DID = 0x4b, /* Device ID Register */ |
| 35 | CH7301_DSP = 0x56, /* DVI Sync polarity Register */ |
| 36 | }; |
| 37 | |
| 38 | int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C; |
| 39 | |
| 40 | int ch7301_probe(unsigned screen, bool power) |
| 41 | { |
| 42 | u8 value; |
| 43 | |
| 44 | i2c_set_bus_num(ch7301_i2c[screen]); |
| 45 | if (i2c_probe(CH7301_I2C_ADDR)) |
| 46 | return -1; |
| 47 | |
| 48 | value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID); |
| 49 | if (value != 0x17) |
| 50 | return -1; |
| 51 | |
| 52 | if (power) { |
| 53 | i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08); |
| 54 | i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16); |
| 55 | i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60); |
| 56 | i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09); |
| 57 | i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0); |
| 58 | } else { |
| 59 | i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x00); |
| 60 | i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0x01); |
| 61 | } |
| 62 | |
| 63 | return 0; |
| 64 | } |