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git01.mediatek.com / filogic / uboot / b34d39ba3eccb048c1ca6dcb5b9867fc7e5db3af / . / doc / device-tree-bindings / ram / fsl,mpc83xx-mem-controller.txt
blob: de498aca7847075beeb2f4afd56c3e9eaefadc26 [file] [log] [blame]
Mario Six538b5752018-08-06 10:23:30 +0200[diff] [blame]1MPC83xx RAM controller
2
3This driver supplies support for the embedded RAM controller on MCP83xx-series
4SoCs.
5
6For static configuration mode, each controller node should have child nodes
7describing the actual RAM modules installed.
8
9Controller node
10===============
11
12Required properties:
13- compatible: Must be "fsl,mpc83xx-mem-controller"
14- reg: The address of the RAM controller's register space
15- #address-cells: Must be 2
16- #size-cells: Must be 1
17- driver_software_override: DDR driver software override is enabled (1) or
18 disabled (0)
19- p_impedance_override: DDR driver software p-impedance override; possible
20 values:
21 * DSO_P_IMPEDANCE_HIGHEST_Z
22 * DSO_P_IMPEDANCE_MUCH_HIGHER_Z
23 * DSO_P_IMPEDANCE_HIGHER_Z
24 * DSO_P_IMPEDANCE_NOMINAL
25 * DSO_P_IMPEDANCE_LOWER_Z
26- n_impedance_override: DDR driver software n-impedance override; possible
27 values:
28 * DSO_N_IMPEDANCE_HIGHEST_Z
29 * DSO_N_IMPEDANCE_MUCH_HIGHER_Z
30 * DSO_N_IMPEDANCE_HIGHER_Z
31 * DSO_N_IMPEDANCE_NOMINAL
32 * DSO_N_IMPEDANCE_LOWER_Z
33- odt_termination_value: ODT termination value for I/Os; possible values:
34 * ODT_TERMINATION_75_OHM
35 * ODT_TERMINATION_150_OHM
36- ddr_type: Selects voltage level for DDR pads; possible
37 values:
38 * DDR_TYPE_DDR2_1_8_VOLT
39 * DDR_TYPE_DDR1_2_5_VOLT
40- mvref_sel: Determine where MVREF_SEL signal is generated;
41 possible values:
42 * MVREF_SEL_EXTERNAL
43 * MVREF_SEL_INTERNAL_GVDD
44- m_odr: Disable memory transaction reordering; possible
45 values:
46 * M_ODR_ENABLE
47 * M_ODR_DISABLE
48- clock_adjust: Clock adjust; possible values:
49 * CLOCK_ADJUST_025
50 * CLOCK_ADJUST_05
51 * CLOCK_ADJUST_075
52 * CLOCK_ADJUST_1
53- ext_refresh_rec: Extended refresh recovery time; possible values:
54 0, 16, 32, 48, 64, 80, 96, 112
55- read_to_write: Read-to-write turnaround; possible values:
56 0, 1, 2, 3
57- write_to_read: Write-to-read turnaround; possible values:
58 0, 1, 2, 3
59- read_to_read: Read-to-read turnaround; possible values:
60 0, 1, 2, 3
61- write_to_write: Write-to-write turnaround; possible values:
62 0, 1, 2, 3
63- active_powerdown_exit: Active powerdown exit timing; possible values:
64 1, 2, 3, 4, 5, 6, 7
65- precharge_powerdown_exit: Precharge powerdown exit timing; possible values:
66 1, 2, 3, 4, 5, 6, 7
67- odt_powerdown_exit: ODT powerdown exit timing; possible values:
68 0, 1, 2, 3, 4, 5, 6, 7, 8,
69 9, 10, 11, 12, 13, 14, 15
70- mode_reg_set_cycle: Mode register set cycle time; possible values:
71 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
72- precharge_to_activate: Precharge-to-acitvate interval; possible values:
73 1, 2, 3, 4, 5, 6, 7
74- activate_to_precharge: Activate to precharge interval; possible values:
75 4, 5, 6, 7, 8, 9, 10, 11, 12,
76 13, 14, 15, 16, 17, 18, 19
77- activate_to_readwrite: Activate to read/write interval for SDRAM;
78 possible values:
79 1, 2, 3, 4, 5, 6, 7
80- mcas_latency: MCAS latency from READ command; possible values:
81 * CASLAT_20
82 * CASLAT_25
83 * CASLAT_30
84 * CASLAT_35
85 * CASLAT_40
86 * CASLAT_45
87 * CASLAT_50
88 * CASLAT_55
89 * CASLAT_60
90 * CASLAT_65
91 * CASLAT_70
92 * CASLAT_75
93 * CASLAT_80
94- refresh_recovery: Refresh recovery time; possible values:
95 8, 9, 10, 11, 12, 13, 14, 15,
96 16, 17, 18, 19, 20, 21, 22, 23
97- last_data_to_precharge: Last data to precharge minimum interval; possible
98 values:
99 1, 2, 3, 4, 5, 6, 7
100- activate_to_activate: Activate-to-activate interval; possible values:
101 1, 2, 3, 4, 5, 6, 7
102- last_write_data_to_read: Last write data pair to read command issue
103 interval; possible values:
104 1, 2, 3, 4, 5, 6, 7
105- additive_latency: Additive latency; possible values:
106 0, 1, 2, 3, 4, 5
107- mcas_to_preamble_override: MCAS-to-preamble-override; possible values:
108 * READ_LAT
109 * READ_LAT_PLUS_1_4
110 * READ_LAT_PLUS_1_2
111 * READ_LAT_PLUS_3_4
112 * READ_LAT_PLUS_1
113 * READ_LAT_PLUS_5_4
114 * READ_LAT_PLUS_3_2
115 * READ_LAT_PLUS_7_4
116 * READ_LAT_PLUS_2
117 * READ_LAT_PLUS_9_4
118 * READ_LAT_PLUS_5_2
119 * READ_LAT_PLUS_11_4
120 * READ_LAT_PLUS_3
121 * READ_LAT_PLUS_13_4
122 * READ_LAT_PLUS_7_2
123 * READ_LAT_PLUS_15_4
124 * READ_LAT_PLUS_4
125 * READ_LAT_PLUS_17_4
126 * READ_LAT_PLUS_9_2
127 * READ_LAT_PLUS_19_4
128- write_latency: Write latency; possible values:
129 1, 2, 3, 4, 5, 6, 7
130- read_to_precharge: Read to precharge; possible values:
131 1, 2, 3, 4
132- write_cmd_to_write_data: Write command to write data strobe timing
133 adjustment; possible values:
134 * CLOCK_DELAY_0
135 * CLOCK_DELAY_1_4
136 * CLOCK_DELAY_1_2
137 * CLOCK_DELAY_3_4
138 * CLOCK_DELAY_1
139 * CLOCK_DELAY_5_4
140 * CLOCK_DELAY_3_2
141- minimum_cke_pulse_width: Minimum CKE pulse width; possible values:
142 1, 2, 3, 4
143- four_activates_window: Window for four activates; possible values:
144 1, 2, 3, 4 8, 9, 10, 11, 12,
145 13, 14, 15, 16, 17, 18, 19
146- self_refresh: Self refresh (during sleep); possible values:
147 * SREN_DISABLE
148 * SREN_ENABLE
149- ecc: Support for ECC; possible values:
150 * ECC_DISABLE
151 * ECC_ENABLE
152- registered_dram: Support for registered DRAM; possible values:
153 * RD_DISABLE
154 * RD_ENABLE
155- sdram_type: Type of SDRAM device to be used; possible values:
156 * TYPE_DDR1
157 * TYPE_DDR2
158- dynamic_power_management: Dynamic power management mode; possible values:
159 * DYN_PWR_DISABLE
160 * DYN_PWR_ENABLE
161- databus_width: DRAM data bus width; possible values
162 * DATA_BUS_WIDTH_16
163 * DATA_BUS_WIDTH_32
164- nc_auto_precharge: Non-concurrent auto-precharge; possible values:
165 * NCAP_DISABLE
166 * NCAP_ENABLE
167- timing_2t: 2T timing; possible values:
168 * TIMING_1T
169 * TIMING_2T
170- bank_interleaving_ctrl: Bank (chip select) interleaving control; possible
171 values:
172 * INTERLEAVE_NONE
173 * INTERLEAVE_1_AND_2
174- precharge_bit_8: Precharge bin 8; possible values
175 * PRECHARGE_MA_10
176 * PRECHARGE_MA_8
177- half_strength: Global half-strength override; possible values:
178 * STRENGTH_FULL
179 * STRENGTH_HALF
180- bypass_initialization: Bypass initialization; possible values:
181 * INITIALIZATION_DONT_BYPASS
182 * INITIALIZATION_BYPASS
183- force_self_refresh: Force self refresh; possible values:
184 * MODE_NORMAL
185 * MODE_REFRESH
186- dll_reset: DLL reset; possible values:
187 * DLL_RESET_ENABLE
188 * DLL_RESET_DISABLE
189- dqs_config: DQS configuration; possible values:
190 * DQS_TRUE
191- odt_config: ODT configuration; possible values:
192 * ODT_ASSERT_NEVER
193 * ODT_ASSERT_WRITES
194 * ODT_ASSERT_READS
195 * ODT_ASSERT_ALWAYS
196- posted_refreshes: Number of posted refreshes
197 1, 2, 3, 4, 5, 6, 7, 8
198- sdmode: Initial value loaded into the DDR SDRAM mode
199 register
200- esdmode: Initial value loaded into the DDR SDRAM extended
201 mode register
202- esdmode2: Initial value loaded into the DDR SDRAM extended
203 mode 2 register
204- esdmode3: Initial value loaded into the DDR SDRAM extended
205 mode 3 register
206- refresh_interval: Refresh interval; possible values:
207 0 - 65535
208- precharge_interval: Precharge interval; possible values:
209 0 - 16383
210
211RAM module node:
212================
213
214Required properties:
215- reg: A triple <cs addr size>, which consists of:
216 * cs - the chipselect used to drive this RAM module
217 * addr - the address where this RAM module's memory is map
218 to in the global memory space
219 * size - the size of the RAM module's memory in bytes
220- auto_precharge: Chip select auto-precharge; possible values:
221 * AUTO_PRECHARGE_ENABLE
222 * AUTO_PRECHARGE_DISABLE
223- odt_rd_cfg: ODT for reads configuration; possible values:
224 * ODT_RD_NEVER
225 * ODT_RD_ONLY_CURRENT
226 * ODT_RD_ONLY_OTHER_CS
227 * ODT_RD_ONLY_OTHER_DIMM
228 * ODT_RD_ALL
229- odt_wr_cfg: ODT for writes configuration; possible values:
230 * ODT_WR_NEVER
231 * ODT_WR_ONLY_CURRENT
232 * ODT_WR_ONLY_OTHER_CS
233 * ODT_WR_ONLY_OTHER_DIMM
234 * ODT_WR_ALL
235- bank_bits: Number of bank bits for SDRAM on chip select; possible
236 values:
237 2, 3
238- row_bits: Number of row bits for SDRAM on chip select; possible values:
239 12, 13, 14
240- col_bits: Number of column bits for SDRAM on chip select; possible
241 values:
242 8, 9, 10, 11
243
244Example:
245
246memory@2000 {
247 #address-cells = <2>;
248 #size-cells = <1>;
249 compatible = "fsl,mpc83xx-mem-controller";
250 reg = <0x2000 0x1000>;
251 device_type = "memory";
Simon Glass07a8b622023-02-13 08:56:35 -0700[diff] [blame]252 bootph-all;
Mario Six538b5752018-08-06 10:23:30 +0200[diff] [blame]253
254 driver_software_override = <DSO_ENABLE>;
255 p_impedance_override = <DSO_P_IMPEDANCE_NOMINAL>;
256 n_impedance_override = <DSO_N_IMPEDANCE_NOMINAL>;
257 odt_termination_value = <ODT_TERMINATION_150_OHM>;
258 ddr_type = <DDR_TYPE_DDR2_1_8_VOLT>;
259
260 clock_adjust = <CLOCK_ADJUST_05>;
261
262 read_to_write = <0>;
263 write_to_read = <0>;
264 read_to_read = <0>;
265 write_to_write = <0>;
266 active_powerdown_exit = <2>;
267 precharge_powerdown_exit = <6>;
268 odt_powerdown_exit = <8>;
269 mode_reg_set_cycle = <2>;
270
271 precharge_to_activate = <2>;
272 activate_to_precharge = <6>;
273 activate_to_readwrite = <2>;
274 mcas_latency = <CASLAT_40>;
275 refresh_recovery = <17>;
276 last_data_to_precharge = <2>;
277 activate_to_activate = <2>;
278 last_write_data_to_read = <2>;
279
280 additive_latency = <0>;
281 mcas_to_preamble_override = <READ_LAT_PLUS_1_2>;
282 write_latency = <3>;
283 read_to_precharge = <2>;
284 write_cmd_to_write_data = <CLOCK_DELAY_1_2>;
285 minimum_cke_pulse_width = <3>;
286 four_activates_window = <5>;
287
288 self_refresh = <SREN_ENABLE>;
289 sdram_type = <TYPE_DDR2>;
290 databus_width = <DATA_BUS_WIDTH_32>;
291
292 force_self_refresh = <MODE_NORMAL>;
293 dll_reset = <DLL_RESET_ENABLE>;
294 dqs_config = <DQS_TRUE>;
295 odt_config = <ODT_ASSERT_READS>;
296 posted_refreshes = <1>;
297
298 refresh_interval = <2084>;
299 precharge_interval = <256>;
300
301 sdmode = <0x0242>;
302 esdmode = <0x0440>;
303
304 ram@0 {
305 reg = <0x0 0x0 0x8000000>;
306 compatible = "nanya,nt5tu64m16hg";
307
308 odt_rd_cfg = <ODT_RD_NEVER>;
309 odt_wr_cfg = <ODT_WR_ONLY_CURRENT>;
310 bank_bits = <3>;
311 row_bits = <13>;
312 col_bits = <10>;
313 };
314};