| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| Zubair Lutfullah Kakakhel | 1d153b3 | 2016-07-29 15:11:20 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Imagination Technologies MIPSfpga platform code |
| 4 | * |
| 5 | * Copyright (C) 2016, Imagination Technologies Ltd. |
| 6 | * |
| 7 | * Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> |
| 8 | * |
| Zubair Lutfullah Kakakhel | 1d153b3 | 2016-07-29 15:11:20 +0100 | [diff] [blame] | 9 | */ |
| 10 | |
| Tom Rini | dec7ea0 | 2024-05-20 13:35:03 -0600 | [diff] [blame] | 11 | #include <config.h> |
| Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 12 | #include <init.h> |
| Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 13 | #include <asm/global_data.h> |
| Zubair Lutfullah Kakakhel | 1d153b3 | 2016-07-29 15:11:20 +0100 | [diff] [blame] | 14 | |
| Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 15 | DECLARE_GLOBAL_DATA_PTR; |
| 16 | |
| Zubair Lutfullah Kakakhel | 1d153b3 | 2016-07-29 15:11:20 +0100 | [diff] [blame] | 17 | /* initialize the DDR Controller and PHY */ |
| Simon Glass | d35f338 | 2017-04-06 12:47:05 -0600 | [diff] [blame] | 18 | int dram_init(void) |
| Zubair Lutfullah Kakakhel | 1d153b3 | 2016-07-29 15:11:20 +0100 | [diff] [blame] | 19 | { |
| 20 | /* MIG IP block is smart and doesn't need SW |
| 21 | * to do any init */ |
| Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 22 | gd->ram_size = CFG_SYS_SDRAM_SIZE; /* in bytes */ |
| Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 23 | |
| 24 | return 0; |
| Zubair Lutfullah Kakakhel | 1d153b3 | 2016-07-29 15:11:20 +0100 | [diff] [blame] | 25 | } |