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Gaurav Jain81113a02022-03-24 11:50:27 +05301// SPDX-License-Identifier: GPL-2.0-or-later
Peng Fana181afe2019-09-16 03:09:55 +00002/*
Gaurav Jain81113a02022-03-24 11:50:27 +05303 * Copyright 2018-2019, 2021 NXP
Peng Fana181afe2019-09-16 03:09:55 +00004 *
Peng Fana181afe2019-09-16 03:09:55 +00005 */
6
Simon Glassed38aef2020-05-10 11:40:03 -06007#include <command.h>
Simon Glassafb02152019-12-28 10:45:01 -07008#include <cpu_func.h>
Simon Glassf11478f2019-12-28 10:45:07 -07009#include <hang.h>
Simon Glass2dc9c342020-05-10 11:40:01 -060010#include <image.h>
Simon Glass97589732020-05-10 11:40:02 -060011#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060012#include <log.h>
Peng Fana181afe2019-09-16 03:09:55 +000013#include <spl.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060014#include <asm/global_data.h>
Peng Fana181afe2019-09-16 03:09:55 +000015#include <asm/io.h>
16#include <asm/mach-imx/iomux-v3.h>
17#include <asm/arch/clock.h>
18#include <asm/arch/imx8mn_pins.h>
19#include <asm/arch/sys_proto.h>
20#include <asm/mach-imx/boot_mode.h>
21#include <asm/arch/ddr.h>
Shiji Yangbb112342023-08-03 09:47:16 +080022#include <asm/sections.h>
Peng Fana181afe2019-09-16 03:09:55 +000023
24#include <dm/uclass.h>
25#include <dm/device.h>
26#include <dm/uclass-internal.h>
27#include <dm/device-internal.h>
Peng Fan80607bf2021-03-19 15:57:08 +080028#include <power/pmic.h>
29#include <power/pca9450.h>
30#include <asm/mach-imx/gpio.h>
31#include <asm/mach-imx/mxc_i2c.h>
32#include <fsl_esdhc_imx.h>
33#include <mmc.h>
Peng Fana181afe2019-09-16 03:09:55 +000034
35DECLARE_GLOBAL_DATA_PTR;
36
37int spl_board_boot_device(enum boot_device boot_dev_spl)
38{
39 return BOOT_DEVICE_BOOTROM;
40}
41
42void spl_dram_init(void)
43{
44 ddr_init(&dram_timing);
45}
46
47void spl_board_init(void)
48{
49 struct udevice *dev;
50 int ret;
51
Marek Vasut085555f2022-09-19 21:41:15 +020052 arch_misc_init();
53
Peng Fana181afe2019-09-16 03:09:55 +000054 puts("Normal Boot\n");
55
56 ret = uclass_get_device_by_name(UCLASS_CLK,
57 "clock-controller@30380000",
58 &dev);
59 if (ret < 0)
60 printf("Failed to find clock node. Check device tree\n");
61}
62
Peng Fan80607bf2021-03-19 15:57:08 +080063#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
64int power_init_board(void)
65{
66 struct udevice *dev;
67 int ret;
68
Marcel Ziswilera1033b82022-07-21 15:43:37 +020069 ret = pmic_get("pmic@25", &dev);
Peng Fan80607bf2021-03-19 15:57:08 +080070 if (ret == -ENODEV) {
71 puts("No pca9450@25\n");
72 return 0;
73 }
74 if (ret != 0)
75 return ret;
76
77 /* BUCKxOUT_DVS0/1 control BUCK123 output */
78 pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
79
Ye Liee337ce2021-03-19 15:57:09 +080080#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
81 /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */
82 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10);
83#else
Peng Fan80607bf2021-03-19 15:57:08 +080084 /* increase VDD_SOC/VDD_DRAM to typical value 0.95V before first DRAM access */
Ye Liee337ce2021-03-19 15:57:09 +080085 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
86#endif
Peng Fan80607bf2021-03-19 15:57:08 +080087 /* Set DVS1 to 0.85v for suspend */
88 /* Enable DVS control through PMIC_STBY_REQ and set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */
Peng Fan80607bf2021-03-19 15:57:08 +080089 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
90 pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
91
92 /* set VDD_SNVS_0V8 from default 0.85V */
93 pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
94
95 /* enable LDO4 to 1.2v */
96 pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x44);
97
Peng Fan80607bf2021-03-19 15:57:08 +080098 return 0;
99}
100#endif
101
Peng Fana181afe2019-09-16 03:09:55 +0000102#ifdef CONFIG_SPL_LOAD_FIT
103int board_fit_config_name_match(const char *name)
104{
105 /* Just empty function now - can't decide what to choose */
106 debug("%s: %s\n", __func__, name);
107
108 return 0;
109}
110#endif
111
Peng Fana181afe2019-09-16 03:09:55 +0000112void board_init_f(ulong dummy)
113{
114 int ret;
115
116 arch_cpu_init();
117
118 init_uart_clk(1);
119
Peng Fana181afe2019-09-16 03:09:55 +0000120 timer_init();
121
Peng Fana181afe2019-09-16 03:09:55 +0000122 /* Clear the BSS. */
123 memset(__bss_start, 0, __bss_end - __bss_start);
124
125 ret = spl_init();
126 if (ret) {
127 debug("spl_init() failed: %d\n", ret);
128 hang();
129 }
130
Peng Fanbee25f12022-04-15 12:35:35 +0800131 preloader_console_init();
132
Peng Fana181afe2019-09-16 03:09:55 +0000133 enable_tzc380();
134
135 /* DDR initialization */
136 spl_dram_init();
137
138 board_init_r(NULL, 0);
139}