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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2002
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 * Keith Outwater, keith_outwater@mvis.com
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00007 */
8
9#ifndef _VIRTEX2_H_
10#define _VIRTEX2_H_
11
12#include <xilinx.h>
13
Wolfgang Denk74f9b382011-07-30 13:33:49 +000014extern int Virtex2_load(Xilinx_desc *desc, const void *image, size_t size);
15extern int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
16extern int Virtex2_info(Xilinx_desc *desc);
wdenkc6097192002-11-03 00:24:07 +000017
18/*
19 * Slave SelectMap Implementation function table.
20 */
21typedef struct {
22 Xilinx_pre_fn pre;
23 Xilinx_pgm_fn pgm;
24 Xilinx_init_fn init;
25 Xilinx_err_fn err;
26 Xilinx_done_fn done;
27 Xilinx_clk_fn clk;
28 Xilinx_cs_fn cs;
29 Xilinx_wr_fn wr;
30 Xilinx_rdata_fn rdata;
31 Xilinx_wdata_fn wdata;
32 Xilinx_busy_fn busy;
33 Xilinx_abort_fn abort;
34 Xilinx_post_fn post;
wdenkc6097192002-11-03 00:24:07 +000035} Xilinx_Virtex2_Slave_SelectMap_fns;
36
37/* Slave Serial Implementation function table */
38typedef struct {
39 Xilinx_pgm_fn pgm;
40 Xilinx_clk_fn clk;
41 Xilinx_rdata_fn rdata;
42 Xilinx_wdata_fn wdata;
wdenkc6097192002-11-03 00:24:07 +000043} Xilinx_Virtex2_Slave_Serial_fns;
44
45/* Device Image Sizes (in bytes)
46 *********************************************************************/
47#define XILINX_XC2V40_SIZE (338208 / 8)
48#define XILINX_XC2V80_SIZE (597408 / 8)
49#define XILINX_XC2V250_SIZE (1591584 / 8)
50#define XILINX_XC2V500_SIZE (2557857 / 8)
51#define XILINX_XC2V1000_SIZE (3749408 / 8)
52#define XILINX_XC2V1500_SIZE (5166240 / 8)
53#define XILINX_XC2V2000_SIZE (6808352 / 8)
54#define XILINX_XC2V3000_SIZE (9589408 / 8)
55#define XILINX_XC2V4000_SIZE (14220192 / 8)
56#define XILINX_XC2V6000_SIZE (19752096 / 8)
57#define XILINX_XC2V8000_SIZE (26185120 / 8)
58#define XILINX_XC2V10000_SIZE (33519264 / 8)
59
60/* Descriptor Macros
61 *********************************************************************/
62#define XILINX_XC2V40_DESC(iface, fn_table, cookie) \
63{ Xilinx_Virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie }
64
65#define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
66{ Xilinx_Virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie }
67
68#define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
69{ Xilinx_Virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie }
70
71#define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
72{ Xilinx_Virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie }
73
74#define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
75{ Xilinx_Virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie }
76
77#define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
78{ Xilinx_Virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie }
79
80#define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
81{ Xilinx_Virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie }
82
83#define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
84{ Xilinx_Virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie }
85
86#define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
87{ Xilinx_Virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie }
88
89#define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
90{ Xilinx_Virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie }
91
92#define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
93{ Xilinx_Virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie }
94
95#define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
96{ Xilinx_Virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie }
97
98#endif /* _VIRTEX2_H_ */