blob: 191f2a5f301e2f8a817cb01a803852a2eb6cff49 [file] [log] [blame]
Tinghui Wang131bffe2014-08-28 21:16:40 +10001/*
2 * (C) Copyright 2012 Xilinx
3 * (C) Copyright 2014 Digilent Inc.
4 *
5 * Configuration for Zynq Development Board - ZYBO
6 * See zynq-common.h for Zynq common configs
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#ifndef __CONFIG_ZYNQ_ZYBO_H
12#define __CONFIG_ZYNQ_ZYBO_H
13
14#define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024)
15
16#define CONFIG_ZYNQ_SERIAL_UART1
17#define CONFIG_ZYNQ_GEM0
18#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0
19
20#define CONFIG_SYS_NO_FLASH
21
22#define CONFIG_ZYNQ_SDHCI0
23#define CONFIG_ZYNQ_BOOT_FREEBSD
Tinghui Wang131bffe2014-08-28 21:16:40 +100024
25/* Define ZYBO PS Clock Frequency to 50MHz */
26#define CONFIG_ZYNQ_PS_CLK_FREQ 50000000UL
27
28#include <configs/zynq-common.h>
29
30#endif /* __CONFIG_ZYNQ_ZYBO_H */