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Andreas Bießmann1a1d61d2012-09-04 11:33:29 +00001/*
2 * Copyright (C) 2006 Atmel Corporation
3 *
4 * Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com>
5 *
6 * Configuration settings for the AVR32 Network Gateway
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Andreas Bießmann1a1d61d2012-09-04 11:33:29 +00009 */
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#include <asm/arch/hardware.h>
14
Andreas Bießmann1a1d61d2012-09-04 11:33:29 +000015#define CONFIG_AT32AP
16#define CONFIG_AT32AP7000
17#define CONFIG_ATNGW100MKII
18
Andreas Bießmann9f7a53e2015-03-01 22:01:13 +010019#define CONFIG_SYS_GENERIC_BOARD
20#define CONFIG_BOARD_EARLY_INIT_F
21#define CONFIG_BOARD_EARLY_INIT_R
22
Andreas Bießmann1a1d61d2012-09-04 11:33:29 +000023/*
Andreas Bießmann1a1d61d2012-09-04 11:33:29 +000024 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
25 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
26 * and the PBA bus to run at 1/4 the PLL frequency.
27 */
28#define CONFIG_PLL
29#define CONFIG_SYS_POWER_MANAGER
30#define CONFIG_SYS_OSC0_HZ 20000000
31#define CONFIG_SYS_PLL0_DIV 1
32#define CONFIG_SYS_PLL0_MUL 7
33#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
34/*
35 * Set the CPU running at:
36 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
37 */
38#define CONFIG_SYS_CLKDIV_CPU 0
39/*
40 * Set the HSB running at:
41 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
42 */
43#define CONFIG_SYS_CLKDIV_HSB 1
44/*
45 * Set the PBA running at:
46 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
47 */
48#define CONFIG_SYS_CLKDIV_PBA 2
49/*
50 * Set the PBB running at:
51 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
52 */
53#define CONFIG_SYS_CLKDIV_PBB 1
54
55/* Reserve VM regions for NOR flash, NAND flash and SDRAM */
56#define CONFIG_SYS_NR_VM_REGIONS 3
57
58/*
59 * The PLLOPT register controls the PLL like this:
60 * icp = PLLOPT<2>
61 * ivco = PLLOPT<1:0>
62 *
63 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
64 */
65#define CONFIG_SYS_PLL0_OPT 0x04
66
67#define CONFIG_USART_BASE ATMEL_BASE_USART1
68#define CONFIG_USART_ID 1
69
70/* User serviceable stuff */
71#define CONFIG_DOS_PARTITION
72
73#define CONFIG_CMDLINE_TAG
74#define CONFIG_SETUP_MEMORY_TAGS
75#define CONFIG_INITRD_TAG
76
77#define CONFIG_STACKSIZE (2048)
78
79#define CONFIG_BAUDRATE 115200
80#define CONFIG_BOOTARGS \
81 "root=mtd:main rootfstype=jffs2"
82#define CONFIG_BOOTCOMMAND \
83 "fsload 0x10400000 /uImage; bootm"
84
85/*
86 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
87 * data on the serial line may interrupt the boot sequence.
88 */
89#define CONFIG_BOOTDELAY 1
90#define CONFIG_AUTOBOOT
91#define CONFIG_AUTOBOOT_KEYED
92#define CONFIG_AUTOBOOT_PROMPT \
93 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
94#define CONFIG_AUTOBOOT_DELAY_STR "d"
95#define CONFIG_AUTOBOOT_STOP_STR " "
96
97/*
98 * After booting the board for the first time, new ethernet addresses
99 * should be generated and assigned to the environment variables
100 * "ethaddr" and "eth1addr". This is normally done during production.
101 */
102#define CONFIG_OVERWRITE_ETHADDR_ONCE
103#define CONFIG_NET_MULTI
104
105/*
106 * BOOTP/DHCP options
107 */
108#define CONFIG_BOOTP_SUBNETMASK
109#define CONFIG_BOOTP_GATEWAY
110
111/*
112 * Command line configuration.
113 */
114#include <config_cmd_default.h>
115
116#define CONFIG_CMD_ASKENV
117#define CONFIG_CMD_DHCP
118#define CONFIG_CMD_EXT2
119#define CONFIG_CMD_FAT
120#define CONFIG_CMD_JFFS2
121#define CONFIG_CMD_MMC
122#define CONFIG_CMD_SF
123#define CONFIG_CMD_SPI
124#define CONFIG_CMD_MII
125
126#undef CONFIG_CMD_FPGA
127#undef CONFIG_CMD_SETGETDCR
128#undef CONFIG_CMD_XIMG
129
130#define CONFIG_ATMEL_USART
131#define CONFIG_MACB
132#define CONFIG_PORTMUX_PIO
133#define CONFIG_SYS_NR_PIOS 5
134#define CONFIG_SYS_HSDRAMC
135#define CONFIG_MMC
136#define CONFIG_GENERIC_ATMEL_MCI
137#define CONFIG_GENERIC_MMC
Andreas Bießmann1a1d61d2012-09-04 11:33:29 +0000138#define CONFIG_ATMEL_SPI
139
140#define CONFIG_SPI_FLASH
141#define CONFIG_SPI_FLASH_ATMEL
142
143#define CONFIG_SYS_DCACHE_LINESZ 32
144#define CONFIG_SYS_ICACHE_LINESZ 32
145
146#define CONFIG_NR_DRAM_BANKS 1
147
148#define CONFIG_SYS_FLASH_CFI
149#define CONFIG_FLASH_CFI_DRIVER
150#define CONFIG_SYS_FLASH_PROTECTION
151
152#define CONFIG_SYS_FLASH_BASE 0x00000000
153#define CONFIG_SYS_FLASH_SIZE 0x800000
154#define CONFIG_SYS_MAX_FLASH_BANKS 1
155#define CONFIG_SYS_MAX_FLASH_SECT 135
156
157#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Andreas Bießmann07a08d72014-05-16 12:17:41 +0200158#define CONFIG_SYS_TEXT_BASE 0x00000000
Andreas Bießmann1a1d61d2012-09-04 11:33:29 +0000159
160#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
161#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
162#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
163
164#define CONFIG_ENV_IS_IN_FLASH
165#define CONFIG_ENV_SIZE 65536
166#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
167
168#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
169
170#define CONFIG_SYS_MALLOC_LEN (256*1024)
Andreas Bießmann1a1d61d2012-09-04 11:33:29 +0000171
172/* Allow 4MB for the kernel run-time image */
173#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
174#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
175
176/* Other configuration settings that shouldn't have to change all that often */
177#define CONFIG_SYS_PROMPT "U-Boot> "
178#define CONFIG_SYS_CBSIZE 256
179#define CONFIG_SYS_MAXARGS 16
180#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
181#define CONFIG_SYS_LONGHELP
182
183#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
184#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
185
186#define CONFIG_MTD_DEVICE
187#define CONFIG_MTD_PARTITIONS
188
189#endif /* __CONFIG_H */