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git01.mediatek.com / filogic / uboot / 75d38e7bbd61347a3957ab9e2fb341d800285757 / . / board / compal / paz00 / paz00.c
blob: 43931b0653a3f414a7399b8f33290951244d1d0a [file] [log] [blame]
Stephen Warrenf5dc27a2012-01-06 12:14:42 +0000[diff] [blame]1/*
2 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
Tom Rinie2378802016-01-14 22:05:13 -0500[diff] [blame]7 * SPDX-License-Identifier: GPL-2.0
Stephen Warrenf5dc27a2012-01-06 12:14:42 +0000[diff] [blame]8 */
9
10#include <common.h>
11#include <asm/io.h>
Tom Warrenab371962012-09-19 15:50:56 -0700[diff] [blame]12#include <asm/arch/tegra.h>
Stephen Warrenf5dc27a2012-01-06 12:14:42 +0000[diff] [blame]13#include <asm/arch/pinmux.h>
Stephen Warrenf5dc27a2012-01-06 12:14:42 +0000[diff] [blame]14#include <asm/gpio.h>
Stephen Warrenf5dc27a2012-01-06 12:14:42 +0000[diff] [blame]15
Tom Warren2967d482012-06-01 08:22:14 +0000[diff] [blame]16#ifdef CONFIG_TEGRA_MMC
Stephen Warrenf5dc27a2012-01-06 12:14:42 +0000[diff] [blame]17/*
18 * Routine: pin_mux_mmc
19 * Description: setup the pin muxes/tristate values for the SDMMC(s)
20 */
Tom Warren9745cf82013-02-21 12:31:30 +0000[diff] [blame]21void pin_mux_mmc(void)
Stephen Warrenf5dc27a2012-01-06 12:14:42 +0000[diff] [blame]22{
23 /* SDMMC4: config 3, x8 on 2nd set of pins */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]24 pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4);
25 pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4);
26 pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4);
Stephen Warrenf5dc27a2012-01-06 12:14:42 +0000[diff] [blame]27
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]28 pinmux_tristate_disable(PMUX_PINGRP_ATB);
29 pinmux_tristate_disable(PMUX_PINGRP_GMA);
30 pinmux_tristate_disable(PMUX_PINGRP_GME);
Stephen Warrenf5dc27a2012-01-06 12:14:42 +0000[diff] [blame]31
Lucas Stach2249fb62012-05-16 08:21:01 +0000[diff] [blame]32 /* SDIO1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]33 pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1);
Stephen Warrenf5dc27a2012-01-06 12:14:42 +0000[diff] [blame]34
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]35 pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
Stephen Warrenf5dc27a2012-01-06 12:14:42 +0000[diff] [blame]36
37 /* For power GPIO PV1 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]38 pinmux_tristate_disable(PMUX_PINGRP_UAC);
Stephen Warren07dde1e2012-05-15 11:58:11 +0000[diff] [blame]39 /* For CD GPIO PV5 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]40 pinmux_tristate_disable(PMUX_PINGRP_GPV);
Stephen Warrenf5dc27a2012-01-06 12:14:42 +0000[diff] [blame]41}
Stephen Warrenf5dc27a2012-01-06 12:14:42 +0000[diff] [blame]42#endif
Marc Dietrichb81dfe12012-11-25 11:26:12 +0000[diff] [blame]43
Simon Glasse865ef32016-01-30 16:37:56 -0700[diff] [blame]44#ifdef CONFIG_DM_VIDEO
Marc Dietrichb81dfe12012-11-25 11:26:12 +0000[diff] [blame]45/* this is a weak define that we are overriding */
46void pin_mux_display(void)
47{
48 debug("init display pinmux\n");
49
50 /* EN_VDD_PANEL GPIO A4 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]51 pinmux_tristate_disable(PMUX_PINGRP_DAP2);
Marc Dietrichb81dfe12012-11-25 11:26:12 +0000[diff] [blame]52}
53#endif