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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Bo Shen42aafb32012-07-05 17:21:46 +00002/*
3 * Copyright (C) 2012 Atmel Corporation
4 *
5 * Configuation settings for the AT91SAM9X5EK board.
Bo Shen42aafb32012-07-05 17:21:46 +00006 */
7
8#ifndef __CONFIG_H__
9#define __CONFIG_H__
10
Bo Shen42aafb32012-07-05 17:21:46 +000011/* ARM asynchronous clock */
12#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
13#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
Bo Shen42aafb32012-07-05 17:21:46 +000014
Bo Shen42aafb32012-07-05 17:21:46 +000015/* general purpose I/O */
Bo Shen42aafb32012-07-05 17:21:46 +000016
Bo Shen42aafb32012-07-05 17:21:46 +000017/*
Tom Riniceed5d22017-05-12 22:33:27 -040018 * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0)
Richard Genoud1e34e832012-11-29 23:18:34 +000019 * NB: in this case, USB 1.1 devices won't be recognized.
20 */
21
Bo Shen42aafb32012-07-05 17:21:46 +000022/* SDRAM */
Bo Shen42aafb32012-07-05 17:21:46 +000023#define CONFIG_SYS_SDRAM_BASE 0x20000000
24#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
25
Bo Shen42aafb32012-07-05 17:21:46 +000026/* DataFlash */
Bo Shen42aafb32012-07-05 17:21:46 +000027
Bo Shen42aafb32012-07-05 17:21:46 +000028/* NAND flash */
29#ifdef CONFIG_CMD_NAND
Bo Shen42aafb32012-07-05 17:21:46 +000030#define CONFIG_SYS_MAX_NAND_DEVICE 1
31#define CONFIG_SYS_NAND_BASE 0x40000000
32#define CONFIG_SYS_NAND_DBW_8 1
33/* our ALE is AD21 */
34#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
35/* our CLE is AD22 */
36#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
37#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
38#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
Tom Rini00448d22017-07-28 21:31:42 -040039#endif
40
Bo Shen9a3b1fe2015-03-27 14:23:35 +080041/* SPL */
Bo Shen9a3b1fe2015-03-27 14:23:35 +080042
Bo Shen9a3b1fe2015-03-27 14:23:35 +080043#define CONFIG_SYS_MONITOR_LEN (512 << 10)
44
45#define CONFIG_SYS_MASTER_CLOCK 132096000
46#define CONFIG_SYS_AT91_PLLA 0x20c73f03
47#define CONFIG_SYS_MCKR 0x1301
48#define CONFIG_SYS_MCKR_CSS 0x1302
49
Bo Shen42aafb32012-07-05 17:21:46 +000050#endif