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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Dirk Behme7b84a7b2009-01-28 21:39:58 +01002/*
3 * (C) Copyright 2008
4 * Grazvydas Ignotas <notasas@gmail.com>
5 *
6 * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
7 * Richard Woodruff <r-woodruff2@ti.com>
8 * Syed Mohammed Khasim <khasim@ti.com>
9 * Sunil Kumar <sunilsaini05@gmail.com>
10 * Shashi Ranjan <shashiranjanmca05@gmail.com>
11 *
12 * (C) Copyright 2004-2008
13 * Texas Instruments, <www.ti.com>
Dirk Behme7b84a7b2009-01-28 21:39:58 +010014 */
15#include <common.h>
Tom Rix0f2a8042009-06-28 12:52:30 -050016#include <twl4030.h>
Dirk Behme7b84a7b2009-01-28 21:39:58 +010017#include <asm/io.h>
Grazvydas Ignotas43d95382012-03-22 13:49:22 +000018#include <asm/gpio.h>
Tom Rini83922512011-09-03 21:51:25 -040019#include <asm/arch/mmc_host_def.h>
Dirk Behme7b84a7b2009-01-28 21:39:58 +010020#include <asm/arch/mux.h>
Aneesh V1843eca2011-07-31 20:30:53 +000021#include <asm/arch/gpio.h>
Dirk Behme7b84a7b2009-01-28 21:39:58 +010022#include <asm/arch/sys_proto.h>
23#include <asm/mach-types.h>
24#include "pandora.h"
25
John Rigby0d21ed02010-12-20 18:27:51 -070026DECLARE_GLOBAL_DATA_PTR;
27
Grazvydas Ignotas09a22512010-06-08 17:19:22 -040028#define TWL4030_BB_CFG_BBCHEN (1 << 4)
29#define TWL4030_BB_CFG_BBSEL_3200MV (3 << 2)
30#define TWL4030_BB_CFG_BBISEL_500UA 2
31
Grazvydas Ignotas43d95382012-03-22 13:49:22 +000032#define CONTROL_WKUP_CTRL 0x48002a5c
33#define GPIO_IO_PWRDNZ (1 << 6)
34#define PBIASLITEVMODE1 (1 << 8)
35
Tom Rix558bb832009-04-01 22:02:20 -050036/*
Dirk Behme7b84a7b2009-01-28 21:39:58 +010037 * Routine: board_init
38 * Description: Early hardware init.
Tom Rix558bb832009-04-01 22:02:20 -050039 */
Dirk Behme7b84a7b2009-01-28 21:39:58 +010040int board_init(void)
41{
Dirk Behme7b84a7b2009-01-28 21:39:58 +010042 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
43 /* board id for Linux */
44 gd->bd->bi_arch_number = MACH_TYPE_OMAP3_PANDORA;
45 /* boot param addr */
46 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
47
48 return 0;
49}
50
Grazvydas Ignotas43d95382012-03-22 13:49:22 +000051static void set_output_gpio(unsigned int gpio, int value)
52{
53 int ret;
54
55 ret = gpio_request(gpio, "");
56 if (ret != 0) {
57 printf("could not request GPIO %u\n", gpio);
58 return;
59 }
60 ret = gpio_direction_output(gpio, value);
61 if (ret != 0)
62 printf("could not set GPIO %u to %d\n", gpio, value);
63}
64
Tom Rix558bb832009-04-01 22:02:20 -050065/*
Dirk Behme7b84a7b2009-01-28 21:39:58 +010066 * Routine: misc_init_r
67 * Description: Configure board specific parts
Tom Rix558bb832009-04-01 22:02:20 -050068 */
Dirk Behme7b84a7b2009-01-28 21:39:58 +010069int misc_init_r(void)
70{
Grazvydas Ignotas43d95382012-03-22 13:49:22 +000071 t2_t *t2_base = (t2_t *)T2_BASE;
72 u32 pbias_lite;
Dirk Behme7b84a7b2009-01-28 21:39:58 +010073
Grazvydas Ignotas17887bf2009-12-10 17:10:21 +020074 twl4030_led_init(TWL4030_LED_LEDEN_LEDBON);
Dirk Behme7b84a7b2009-01-28 21:39:58 +010075
Grazvydas Ignotas43d95382012-03-22 13:49:22 +000076 /* set up dual-voltage GPIOs to 1.8V */
77 pbias_lite = readl(&t2_base->pbias_lite);
78 pbias_lite &= ~PBIASLITEVMODE1;
79 pbias_lite |= PBIASLITEPWRDNZ1;
80 writel(pbias_lite, &t2_base->pbias_lite);
81 if (get_cpu_family() == CPU_OMAP36XX)
82 writel(readl(CONTROL_WKUP_CTRL) | GPIO_IO_PWRDNZ,
83 CONTROL_WKUP_CTRL);
84
85 /* make sure audio and BT chips are in powerdown state */
86 set_output_gpio(14, 0);
87 set_output_gpio(15, 0);
88 set_output_gpio(118, 0);
89
90 /* enable USB supply */
91 set_output_gpio(164, 1);
Dirk Behme7b84a7b2009-01-28 21:39:58 +010092
Grazvydas Ignotas43d95382012-03-22 13:49:22 +000093 /* wifi needs a short pulse to enter powersave state */
94 set_output_gpio(23, 1);
95 udelay(5000);
96 gpio_direction_output(23, 0);
Dirk Behme7b84a7b2009-01-28 21:39:58 +010097
Grazvydas Ignotas09a22512010-06-08 17:19:22 -040098 /* Enable battery backup capacitor (3.2V, 0.5mA charge current) */
99 twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
Nishanth Menond26a1062013-03-26 05:20:49 +0000100 TWL4030_PM_RECEIVER_BB_CFG,
Grazvydas Ignotas09a22512010-06-08 17:19:22 -0400101 TWL4030_BB_CFG_BBCHEN | TWL4030_BB_CFG_BBSEL_3200MV |
Nishanth Menond26a1062013-03-26 05:20:49 +0000102 TWL4030_BB_CFG_BBISEL_500UA);
Grazvydas Ignotas09a22512010-06-08 17:19:22 -0400103
Paul Kocialkowski6bc318e2015-08-27 19:37:13 +0200104 omap_die_id_display();
Dirk Behme12dbcf62009-03-12 19:30:50 +0100105
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100106 return 0;
107}
108
Tom Rix558bb832009-04-01 22:02:20 -0500109/*
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100110 * Routine: set_muxconf_regs
111 * Description: Setting up the configuration Mux registers specific to the
112 * hardware. Many pins need to be moved from protect to primary
113 * mode.
Tom Rix558bb832009-04-01 22:02:20 -0500114 */
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100115void set_muxconf_regs(void)
116{
117 MUX_PANDORA();
Grazvydas Ignotasb5f9c3f2012-03-22 13:49:21 +0000118 if (get_cpu_family() == CPU_OMAP36XX) {
119 MUX_PANDORA_3730();
120 }
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100121}
Tom Rini83922512011-09-03 21:51:25 -0400122
Masahiro Yamada0a780172017-05-09 20:31:39 +0900123#ifdef CONFIG_MMC
Tom Rini83922512011-09-03 21:51:25 -0400124int board_mmc_init(bd_t *bis)
125{
Nikita Kiryanov4be9dbc2012-12-03 02:19:47 +0000126 return omap_mmc_init(0, 0, 0, -1, -1);
Tom Rini83922512011-09-03 21:51:25 -0400127}
Paul Kocialkowski69559892014-11-08 20:55:47 +0100128
129void board_mmc_power_init(void)
130{
131 twl4030_power_mmc_init(0);
132}
Tom Rini83922512011-09-03 21:51:25 -0400133#endif