blob: 8c68372026e9f089df5062bb9430ab5fc1751105 [file] [log] [blame]
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +01001/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#ifndef __VCOREIII_H
7#define __VCOREIII_H
8
9#include <linux/sizes.h>
10
11/* Onboard devices */
12
Horatiu Vultur43be1972019-04-03 19:54:45 +020013#define CONFIG_SYS_MALLOC_LEN 0x1F0000
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +010014#define CONFIG_SYS_LOAD_ADDR 0x00100000
15#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
16
Horatiu Vultur914e7872019-01-23 16:39:42 +010017#if defined(CONFIG_SOC_LUTON) || defined(CONFIG_SOC_SERVAL)
18#define CPU_CLOCK_RATE 416666666 /* Clock for the MIPS core */
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +010019#define CONFIG_SYS_MIPS_TIMER_FREQ 208333333
20#else
Horatiu Vultur914e7872019-01-23 16:39:42 +010021#define CPU_CLOCK_RATE 500000000 /* Clock for the MIPS core */
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +010022#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
23#endif
24#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
25
Lars Povlsen90392822018-12-20 09:56:05 +010026#define CONFIG_BOARD_TYPES
27
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +010028#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
29#define CONFIG_ENV_OFFSET (1024 * 1024)
Horatiu Vultur5f0df582019-04-08 13:32:18 +020030#define CONFIG_ENV_SIZE (8 * 1024)
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +010031#define CONFIG_ENV_SECT_SIZE (256 * 1024)
32
33#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
34#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
35#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
36
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +010037#endif
38
39#define CONFIG_SYS_SDRAM_BASE 0x80000000
40#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ)
41#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M)
42#elif defined(CONFIG_DDRTYPE_MT41J128M16HA) || defined(CONFIG_DDRTYPE_MT41K128M16JT)
43#define CONFIG_SYS_SDRAM_SIZE (256 * SZ_1M)
44#elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) || defined(CONFIG_DDRTYPE_MT41K256M16)
45#define CONFIG_SYS_SDRAM_SIZE (512 * SZ_1M)
46#else
47#error Unknown DDR size - please add!
48#endif
49
50#define CONFIG_CONS_INDEX 1
51
52#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
53#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - SZ_1M)
54
55#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
56
57#define CONFIG_BOARD_EARLY_INIT_R
58#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT)
59#define VCOREIII_DEFAULT_MTD_ENV \
60 "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \
61 "mtdids="CONFIG_MTDIDS_DEFAULT"\0"
62#else
63#define VCOREIII_DEFAULT_MTD_ENV /* Go away */
64#endif
65
66#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
67
68#define CONFIG_EXTRA_ENV_SETTINGS \
69 VCOREIII_DEFAULT_MTD_ENV \
70 "loadaddr=0x81000000\0" \
71 "spi_image_off=0x00100000\0" \
72 "console=ttyS0,115200\0" \
73 "setup=setenv bootargs console=${console} ${mtdparts}" \
74 "${bootargs_extra}\0" \
75 "spiboot=run setup; sf probe; sf read ${loadaddr}" \
76 "${spi_image_off} 0x600000; bootm ${loadaddr}\0" \
77 "ubootfile=u-boot.bin\0" \
78 "update=sf probe;mtdparts;dhcp ${loadaddr} ${ubootfile};" \
79 "sf erase UBoot 0x100000;" \
80 "sf write ${loadaddr} UBoot ${filesize}\0" \
81 "bootcmd=run spiboot\0" \
82 ""
83#endif /* __VCOREIII_H */