blob: f7e3889df07ef4a25181675bb5b3dd14b0dbe79b [file] [log] [blame]
wdenk591dda52002-11-18 00:14:45 +00001/*
Wolfgang Denkf710efd2010-07-24 20:22:02 +02002 * (C) Copyright 2002-2010
wdenk591dda52002-11-18 00:14:45 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk591dda52002-11-18 00:14:45 +00006 */
7
8#ifndef __ASM_GBL_DATA_H
9#define __ASM_GBL_DATA_H
Simon Glass3ac47d72012-12-13 20:48:30 +000010
11#ifndef __ASSEMBLY__
12
Simon Glass30580fc2014-11-12 22:42:23 -070013enum pei_boot_mode_t {
14 PEI_BOOT_NONE = 0,
15 PEI_BOOT_SOFT_RESET,
16 PEI_BOOT_RESUME,
17
18};
19
Simon Glass268eefd2014-11-12 22:42:28 -070020struct memory_area {
21 uint64_t start;
22 uint64_t size;
23};
24
25struct memory_info {
26 int num_areas;
27 uint64_t total_memory;
28 uint64_t total_32bit_memory;
29 struct memory_area area[CONFIG_NR_DRAM_BANKS];
30};
31
Simon Glass7bf5b9e2015-01-01 16:18:07 -070032#define MAX_MTRR_REQUESTS 8
33
34/**
35 * A request for a memory region to be set up in a particular way. These
36 * requests are processed before board_init_r() is called. They are generally
37 * optional and can be ignored with some performance impact.
38 */
39struct mtrr_request {
40 int type; /* MTRR_TYPE_... */
41 uint64_t start;
42 uint64_t size;
43};
44
Simon Glass3ac47d72012-12-13 20:48:30 +000045/* Architecture-specific global data */
46struct arch_global_data {
Bin Meng47eac042015-01-22 11:29:40 +080047 struct global_data *gd_addr; /* Location of Global Data */
48 uint8_t x86; /* CPU family */
49 uint8_t x86_vendor; /* CPU vendor */
50 uint8_t x86_model;
51 uint8_t x86_mask;
Bin Meng035c1d22014-11-09 22:18:56 +080052 uint32_t x86_device;
Simon Glass6fa6e4a2013-02-28 19:26:12 +000053 uint64_t tsc_base; /* Initial value returned by rdtsc() */
54 uint32_t tsc_base_kclocks; /* Initial tsc as a kclocks value */
55 uint32_t tsc_prev; /* For show_boot_progress() */
Bin Mengaed37bf2014-11-09 22:19:35 +080056 uint32_t tsc_mhz; /* TSC frequency in MHz */
Simon Glass347c05b2013-02-28 19:26:15 +000057 void *new_fdt; /* Relocated FDT */
Simon Glass1f4476c2014-11-06 13:20:10 -070058 uint32_t bist; /* Built-in self test value */
Simon Glass30580fc2014-11-12 22:42:23 -070059 enum pei_boot_mode_t pei_boot_mode;
Simon Glass60af0172014-11-12 22:42:24 -070060 const struct pch_gpio_map *gpio_map; /* board GPIO map */
Simon Glass268eefd2014-11-12 22:42:28 -070061 struct memory_info meminfo; /* Memory information */
Bin Meng005f0af2014-12-12 21:05:31 +080062#ifdef CONFIG_HAVE_FSP
Bin Meng47eac042015-01-22 11:29:40 +080063 void *hob_list; /* FSP HOB list */
Bin Meng005f0af2014-12-12 21:05:31 +080064#endif
Simon Glass7bf5b9e2015-01-01 16:18:07 -070065 struct mtrr_request mtrr_req[MAX_MTRR_REQUESTS];
66 int mtrr_req_count;
Bin Meng47eac042015-01-22 11:29:40 +080067 int has_mtrr;
Simon Glass428dfa42015-01-19 22:16:14 -070068 /* MRC training data to save for the next boot */
69 char *mrc_output;
70 unsigned int mrc_output_len;
Simon Glass2027f2b2015-04-28 20:25:15 -060071 void *gdt; /* Global descriptor table */
Simon Glassf95ad8c2015-08-04 12:33:57 -060072 ulong table; /* Table pointer from previous loader */
Simon Glass3ac47d72012-12-13 20:48:30 +000073};
74
Graeme Russ3c28f482011-09-01 00:48:27 +000075#endif
wdenk591dda52002-11-18 00:14:45 +000076
Simon Glassd3887632012-12-13 20:49:27 +000077#include <asm-generic/global_data.h>
78
79#ifndef __ASSEMBLY__
Simon Glass7f65c092015-07-31 09:31:35 -060080# ifdef CONFIG_EFI_APP
81
82#define gd global_data_ptr
83
84#define DECLARE_GLOBAL_DATA_PTR extern struct global_data *global_data_ptr
85# else
Simon Glass42081ce2013-06-11 11:14:52 -070086static inline __attribute__((no_instrument_function)) gd_t *get_fs_gd_ptr(void)
Graeme Russ35368962011-12-31 22:58:15 +110087{
88 gd_t *gd_ptr;
89
90 asm volatile("fs movl 0, %0\n" : "=r" (gd_ptr));
91
92 return gd_ptr;
93}
94
95#define gd get_fs_gd_ptr()
Graeme Russ5fb91cc2010-10-07 20:03:29 +110096
Simon Glass5d18dc92015-07-31 09:31:28 -060097#define DECLARE_GLOBAL_DATA_PTR
Simon Glass7f65c092015-07-31 09:31:35 -060098# endif
Simon Glass5d18dc92015-07-31 09:31:28 -060099
Graeme Russ5fb91cc2010-10-07 20:03:29 +1100100#endif
101
Gabe Blackef899322012-11-03 11:41:28 +0000102/*
103 * Our private Global Data Flags
104 */
Simon Glass5d18dc92015-07-31 09:31:28 -0600105#define GD_FLG_COLD_BOOT 0x10000 /* Cold Boot */
106#define GD_FLG_WARM_BOOT 0x20000 /* Warm Boot */
wdenk591dda52002-11-18 00:14:45 +0000107
108#endif /* __ASM_GBL_DATA_H */