blob: 4ea046d3e5b654d61c47d05a4f58c01a3389f837 [file] [log] [blame]
Bryan Wu97adb222014-06-24 11:45:29 +09001/*
Alexandre Courbot7f936d42015-07-09 16:33:00 +09002 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
Bryan Wu97adb222014-06-24 11:45:29 +09003 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/* Tegra vpr routines */
18
19#include <common.h>
20#include <asm/io.h>
21#include <asm/arch/tegra.h>
22#include <asm/arch/mc.h>
23
Alexandre Courbot7f936d42015-07-09 16:33:00 +090024#include <fdt_support.h>
25
26static bool _configured;
27
28void config_gpu(void)
Bryan Wu97adb222014-06-24 11:45:29 +090029{
30 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
31
32 /* Turn VPR off */
33 writel(0, &mc->mc_video_protect_size_mb);
34 writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED,
35 &mc->mc_video_protect_reg_ctrl);
36 /* read back to ensure the write went through */
37 readl(&mc->mc_video_protect_reg_ctrl);
Alexandre Courbot7f936d42015-07-09 16:33:00 +090038
39 debug("configured VPR\n");
40
41 _configured = true;
42}
43
44bool vpr_configured(void)
45{
46 return _configured;
Bryan Wu97adb222014-06-24 11:45:29 +090047}
Alexandre Courbot5e270dc2015-07-09 16:33:01 +090048
49#if defined(CONFIG_OF_LIBFDT)
50
51int gpu_enable_node(void *blob, const char *gpupath)
52{
53 int offset;
54
55 if (vpr_configured()) {
56 offset = fdt_path_offset(blob, gpupath);
57 if (offset > 0) {
58 fdt_status_okay(blob, offset);
59 debug("enabled GPU node %s\n", gpupath);
60 }
61 }
62
63 return 0;
64}
65
66#endif