Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / b20a50628f171f1b80b66971478e8d3e14833d92 / . / arch / arm / dts / tegra20-colibri.dts
blob: 3131b9201b7029f012c3e4f80df83663c4697d94 [file] [log] [blame]
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]1/dts-v1/;
2
Tom Warrenf6236152013-02-21 12:31:27 +0000[diff] [blame]3#include "tegra20.dtsi"
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]4
5/ {
6 model = "Toradex Colibri T20";
7 compatible = "toradex,t20", "nvidia,tegra20";
8
Simon Glass0c24f372014-09-04 16:27:35 -0600[diff] [blame]9 chosen {
10 stdout-path = &uarta;
11 };
12
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]13 aliases {
14 usb0 = "/usb@c5008000";
15 usb1 = "/usb@c5000000";
16 usb2 = "/usb@c5004000";
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]17 sdhci0 = "/sdhci@c8000600";
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]18 };
19
20 usb@c5000000 {
21 dr_mode = "otg";
22 };
23
24 usb@c5004000 {
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]25 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
26 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]27 };
28
29 usb@c5008000 {
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]30 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]31 };
32
33 nand-controller@70008000 {
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]34 nvidia,wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]35 nvidia,width = <8>;
36 nvidia,timing = <15 100 25 80 25 10 15 10 100>;
37
38 nand@0 {
39 reg = <0>;
40 compatible = "nand-flash";
41 };
42 };
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]43
44 sdhci@c8000600 {
45 status = "okay";
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]46 cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]47 bus-width = <4>;
48 };
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]49};