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git01.mediatek.com / filogic / uboot / b1eed71ceba40a77eca1493022a5b5c10d96dea4 / . / drivers / clk / renesas / r9a07g044-cpg.c
blob: c8baad1a6c8de4a7a642e78f621b6d7cab0fec77 [file] [log] [blame]
Paul Barker132d7ea2023-10-16 10:25:29 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * RZ/G2L CPG driver
4 *
5 * Copyright (C) 2021-2023 Renesas Electronics Corp.
6 */
7
Paul Barker132d7ea2023-10-16 10:25:29 +0100[diff] [blame]8#include <dm/device.h>
9#include <dt-bindings/clock/r9a07g044-cpg.h>
10#include <linux/clk-provider.h>
11
12#include "rzg2l-cpg.h"
13
14/* Divider tables */
15static const struct clk_div_table dtable_1_8[] = {
16 {0, 1},
17 {1, 2},
18 {2, 4},
19 {3, 8},
20 {0, 0},
21};
22
23static const struct clk_div_table dtable_1_32[] = {
24 {0, 1},
25 {1, 2},
26 {2, 4},
27 {3, 8},
28 {4, 32},
29 {0, 0},
30};
31
32static const struct clk_div_table dtable_16_128[] = {
33 {0, 16},
34 {1, 32},
35 {2, 64},
36 {3, 128},
37 {0, 0},
38};
39
40/* Mux clock tables */
41static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
42static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv", ".pll5_fout1ph0" };
43static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
44static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
45static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
46
47static const struct {
48 struct cpg_core_clk common[56];
49} core_clks = {
50 .common = {
51 /* External Clock Inputs */
52 DEF_INPUT("extal", CLK_EXTAL),
53
54 /* Internal Core Clocks */
55 DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
56 DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
57 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
58 DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
59 DEF_FIXED(".pll2_533", CLK_PLL2_533, CLK_PLL2, 1, 3),
60 DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
61 DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),
62 DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),
63
64 DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
65 DEF_FIXED(".pll5_fout3", CLK_PLL5_FOUT3, CLK_PLL5, 1, 6),
66
67 DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
68
69 DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
70 DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2),
71 DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3),
72 DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2),
73 DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2),
74
75 DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
76 DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10),
77
78 DEF_FIXED(".pll2_533_div2", CLK_PLL2_533_DIV2, CLK_PLL2_533, 1, 2),
79
80 DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
81 DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2),
82 DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
83 DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
84 DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3),
85 DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32),
86
87 DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),
88 DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
89 DEF_MUX_RO(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2, sel_gpu2),
90 DEF_PLL5_FOUTPOSTDIV(".pll5_foutpostdiv", CLK_PLL5_FOUTPOSTDIV, CLK_EXTAL),
91 DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2),
92 DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4, sel_pll5_4),
93 DEF_DIV(".div_dsi_lpclk", CLK_DIV_DSI_LPCLK, CLK_PLL2_533_DIV2,
94 DIVDSILPCLK, dtable_16_128),
95
96 /* Core output clk */
97 DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8),
98 DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32),
99 DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),
100 DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1),
101 DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32),
102 DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2),
103 DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32),
104 DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
105 DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
106 DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, sel_pll6_2),
107 DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
108 DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
109 DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, sel_shdi),
110 DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, sel_shdi),
111 DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
112 DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
113 DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8),
114 DEF_FIXED("M1", R9A07G044_CLK_M1, CLK_PLL5_FOUTPOSTDIV, 1, 1),
115 DEF_FIXED("M2", R9A07G044_CLK_M2, CLK_PLL3_533, 1, 2),
116 DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G044_CLK_M2, 1, 2),
117 DEF_DSI_DIV("DSI_DIV", CLK_DSI_DIV, CLK_SEL_PLL5_4, CLK_SET_RATE_PARENT),
118 DEF_FIXED("M3", R9A07G044_CLK_M3, CLK_DSI_DIV, 1, 1),
119 DEF_FIXED("M4", R9A07G044_CLK_M4, CLK_DIV_DSI_LPCLK, 1, 1),
120 },
121};
122
123static const struct {
124 struct rzg2l_mod_clk common[79];
125} mod_clks = {
126 .common = {
127 DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,
128 0x514, 0),
129 DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
130 0x518, 0),
131 DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
132 0x518, 1),
133 DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1,
134 0x52c, 0),
135 DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
136 0x52c, 1),
137 DEF_MOD("ostm0_pclk", R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0,
138 0x534, 0),
139 DEF_MOD("ostm1_pclk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0,
140 0x534, 1),
141 DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
142 0x534, 2),
143 DEF_MOD("mtu_x_mck", R9A07G044_MTU_X_MCK_MTU3, R9A07G044_CLK_P0,
144 0x538, 0),
145 DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0,
146 0x540, 0),
147 DEF_MOD("poeg_a_clkp", R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0,
148 0x544, 0),
149 DEF_MOD("poeg_b_clkp", R9A07G044_POEG_B_CLKP, R9A07G044_CLK_P0,
150 0x544, 1),
151 DEF_MOD("poeg_c_clkp", R9A07G044_POEG_C_CLKP, R9A07G044_CLK_P0,
152 0x544, 2),
153 DEF_MOD("poeg_d_clkp", R9A07G044_POEG_D_CLKP, R9A07G044_CLK_P0,
154 0x544, 3),
155 DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0,
156 0x548, 0),
157 DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK,
158 0x548, 1),
159 DEF_MOD("wdt1_pclk", R9A07G044_WDT1_PCLK, R9A07G044_CLK_P0,
160 0x548, 2),
161 DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK,
162 0x548, 3),
163 DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1,
164 0x550, 0),
165 DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0,
166 0x550, 1),
167 DEF_MOD("sdhi0_imclk", R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4,
168 0x554, 0),
169 DEF_MOD("sdhi0_imclk2", R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4,
170 0x554, 1),
171 DEF_MOD("sdhi0_clk_hs", R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0,
172 0x554, 2),
173 DEF_MOD("sdhi0_aclk", R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1,
174 0x554, 3),
175 DEF_MOD("sdhi1_imclk", R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4,
176 0x554, 4),
177 DEF_MOD("sdhi1_imclk2", R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4,
178 0x554, 5),
179 DEF_MOD("sdhi1_clk_hs", R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1,
180 0x554, 6),
181 DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1,
182 0x554, 7),
183 DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G,
184 0x558, 0),
185 DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1,
186 0x558, 1),
187 DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
188 0x558, 2),
189 DEF_MOD("cru_sysclk", R9A07G044_CRU_SYSCLK, CLK_M2_DIV2,
190 0x564, 0),
191 DEF_MOD("cru_vclk", R9A07G044_CRU_VCLK, R9A07G044_CLK_M2,
192 0x564, 1),
193 DEF_MOD("cru_pclk", R9A07G044_CRU_PCLK, R9A07G044_CLK_ZT,
194 0x564, 2),
195 DEF_MOD("cru_aclk", R9A07G044_CRU_ACLK, R9A07G044_CLK_M0,
196 0x564, 3),
197 DEF_MOD("dsi_pll_clk", R9A07G044_MIPI_DSI_PLLCLK, R9A07G044_CLK_M1,
198 0x568, 0),
199 DEF_MOD("dsi_sys_clk", R9A07G044_MIPI_DSI_SYSCLK, CLK_M2_DIV2,
200 0x568, 1),
201 DEF_MOD("dsi_aclk", R9A07G044_MIPI_DSI_ACLK, R9A07G044_CLK_P1,
202 0x568, 2),
203 DEF_MOD("dsi_pclk", R9A07G044_MIPI_DSI_PCLK, R9A07G044_CLK_P2,
204 0x568, 3),
205 DEF_MOD("dsi_vclk", R9A07G044_MIPI_DSI_VCLK, R9A07G044_CLK_M3,
206 0x568, 4),
207 DEF_MOD("dsi_lpclk", R9A07G044_MIPI_DSI_LPCLK, R9A07G044_CLK_M4,
208 0x568, 5),
209 DEF_COUPLED("lcdc_a", R9A07G044_LCDC_CLK_A, R9A07G044_CLK_M0,
210 0x56c, 0),
211 DEF_COUPLED("lcdc_p", R9A07G044_LCDC_CLK_P, R9A07G044_CLK_ZT,
212 0x56c, 0),
213 DEF_MOD("lcdc_clk_d", R9A07G044_LCDC_CLK_D, R9A07G044_CLK_M3,
214 0x56c, 1),
215 DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
216 0x570, 0),
217 DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
218 0x570, 1),
219 DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0,
220 0x570, 2),
221 DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0,
222 0x570, 3),
223 DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0,
224 0x570, 4),
225 DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0,
226 0x570, 5),
227 DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0,
228 0x570, 6),
229 DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0,
230 0x570, 7),
231 DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1,
232 0x578, 0),
233 DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1,
234 0x578, 1),
235 DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1,
236 0x578, 2),
237 DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1,
238 0x578, 3),
239 DEF_COUPLED("eth0_axi", R9A07G044_ETH0_CLK_AXI, R9A07G044_CLK_M0,
240 0x57c, 0),
241 DEF_COUPLED("eth0_chi", R9A07G044_ETH0_CLK_CHI, R9A07G044_CLK_ZT,
242 0x57c, 0),
243 DEF_COUPLED("eth1_axi", R9A07G044_ETH1_CLK_AXI, R9A07G044_CLK_M0,
244 0x57c, 1),
245 DEF_COUPLED("eth1_chi", R9A07G044_ETH1_CLK_CHI, R9A07G044_CLK_ZT,
246 0x57c, 1),
247 DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0,
248 0x580, 0),
249 DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0,
250 0x580, 1),
251 DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0,
252 0x580, 2),
253 DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0,
254 0x580, 3),
255 DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0,
256 0x584, 0),
257 DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0,
258 0x584, 1),
259 DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0,
260 0x584, 2),
261 DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0,
262 0x584, 3),
263 DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0,
264 0x584, 4),
265 DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
266 0x588, 0),
267 DEF_MOD("sci1", R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0,
268 0x588, 1),
269 DEF_MOD("rspi0", R9A07G044_RSPI0_CLKB, R9A07G044_CLK_P0,
270 0x590, 0),
271 DEF_MOD("rspi1", R9A07G044_RSPI1_CLKB, R9A07G044_CLK_P0,
272 0x590, 1),
273 DEF_MOD("rspi2", R9A07G044_RSPI2_CLKB, R9A07G044_CLK_P0,
274 0x590, 2),
275 DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0,
276 0x594, 0),
277 DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
278 0x598, 0),
279 DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU,
280 0x5a8, 0),
281 DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0,
282 0x5a8, 1),
283 DEF_MOD("tsu_pclk", R9A07G044_TSU_PCLK, R9A07G044_CLK_TSU,
284 0x5ac, 0),
285 },
286};
287
288static const struct rzg2l_reset r9a07g044_resets[] = {
289 DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
290 DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
291 DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
292 DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
293 DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
294 DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),
295 DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
296 DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
297 DEF_RST(R9A07G044_MTU_X_PRESET_MTU3, 0x838, 0),
298 DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0),
299 DEF_RST(R9A07G044_POEG_A_RST, 0x844, 0),
300 DEF_RST(R9A07G044_POEG_B_RST, 0x844, 1),
301 DEF_RST(R9A07G044_POEG_C_RST, 0x844, 2),
302 DEF_RST(R9A07G044_POEG_D_RST, 0x844, 3),
303 DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
304 DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
305 DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
306 DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),
307 DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),
308 DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),
309 DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),
310 DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),
311 DEF_RST(R9A07G044_CRU_CMN_RSTB, 0x864, 0),
312 DEF_RST(R9A07G044_CRU_PRESETN, 0x864, 1),
313 DEF_RST(R9A07G044_CRU_ARESETN, 0x864, 2),
314 DEF_RST(R9A07G044_MIPI_DSI_CMN_RSTB, 0x868, 0),
315 DEF_RST(R9A07G044_MIPI_DSI_ARESET_N, 0x868, 1),
316 DEF_RST(R9A07G044_MIPI_DSI_PRESET_N, 0x868, 2),
317 DEF_RST(R9A07G044_LCDC_RESET_N, 0x86c, 0),
318 DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
319 DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
320 DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
321 DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3),
322 DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0),
323 DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1),
324 DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2),
325 DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3),
326 DEF_RST(R9A07G044_ETH0_RST_HW_N, 0x87c, 0),
327 DEF_RST(R9A07G044_ETH1_RST_HW_N, 0x87c, 1),
328 DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0),
329 DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1),
330 DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2),
331 DEF_RST(R9A07G044_I2C3_MRST, 0x880, 3),
332 DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0),
333 DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1),
334 DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2),
335 DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
336 DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
337 DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
338 DEF_RST(R9A07G044_SCI1_RST, 0x888, 1),
339 DEF_RST(R9A07G044_RSPI0_RST, 0x890, 0),
340 DEF_RST(R9A07G044_RSPI1_RST, 0x890, 1),
341 DEF_RST(R9A07G044_RSPI2_RST, 0x890, 2),
342 DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0),
343 DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1),
344 DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),
345 DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1),
346 DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),
347 DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),
348 DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),
349 DEF_RST(R9A07G044_TSU_PRESETN, 0x8ac, 0),
350};
351
352const struct rzg2l_cpg_info r9a07g044_cpg_info = {
353 /* Core Clocks */
354 .core_clks = core_clks.common,
355 .num_core_clks = ARRAY_SIZE(core_clks.common),
356
357 /* Module Clocks */
358 .mod_clks = mod_clks.common,
359 .num_mod_clks = ARRAY_SIZE(mod_clks.common),
360 .num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,
361
362 /* Resets */
363 .resets = r9a07g044_resets,
364 .num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */
365
366 .has_clk_mon_regs = true,
367};
368
369static const struct udevice_id r9a07g044_cpg_ids[] = {
370 {
371 .compatible = "renesas,r9a07g044-cpg",
372 .data = (unsigned long)&r9a07g044_cpg_info,
373 },
374 { /* sentinel */ }
375};
376
377U_BOOT_DRIVER(r9a07g044_cpg) = {
378 .name = "r9a07g044-cpg",
379 .id = UCLASS_NOP,
380 .of_match = r9a07g044_cpg_ids,
381 .bind = rzg2l_cpg_bind,
382 .flags = DM_FLAG_PRE_RELOC,
383};