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git01.mediatek.com / filogic / uboot / b1c50fbb717f409e01c5fdc431ef3bd976b51c5e / . / arch / arm / dts / tegra20-paz00.dts
blob: f5edff13496d3c6f2b7ecf56135bf97fbf0f09dd [file] [log] [blame]
Stephen Warren24bfee62012-05-21 10:04:37 +0000[diff] [blame]1/dts-v1/;
2
Tom Warrenf6236152013-02-21 12:31:27 +0000[diff] [blame]3#include "tegra20.dtsi"
Stephen Warren24bfee62012-05-21 10:04:37 +0000[diff] [blame]4
5/ {
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]6 model = "Toshiba AC100 / Dynabook AZ";
7 compatible = "compal,paz00", "nvidia,tegra20";
Stephen Warren24bfee62012-05-21 10:04:37 +0000[diff] [blame]8
Simon Glass0c24f372014-09-04 16:27:35 -0600[diff] [blame]9 chosen {
10 stdout-path = &uarta;
11 };
12
Stephen Warren24bfee62012-05-21 10:04:37 +0000[diff] [blame]13 aliases {
14 usb0 = "/usb@c5008000";
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]15 sdhci0 = "/sdhci@c8000600";
16 sdhci1 = "/sdhci@c8000000";
Stephen Warren24bfee62012-05-21 10:04:37 +0000[diff] [blame]17 };
18
19 memory {
20 reg = <0x00000000 0x20000000>;
21 };
22
Simon Glasse31a2a52016-01-30 16:37:52 -0700[diff] [blame]23 host1x@50000000 {
Allen Martin0398dcb2013-01-16 13:12:24 +0000[diff] [blame]24 status = "okay";
25 dc@54200000 {
26 status = "okay";
27 rgb {
28 status = "okay";
29 nvidia,panel = <&lcd_panel>;
30 };
31 };
32 };
33
Stephen Warren24bfee62012-05-21 10:04:37 +0000[diff] [blame]34 serial@70006000 {
35 clock-frequency = < 216000000 >;
36 };
37
Simon Glasse31a2a52016-01-30 16:37:52 -0700[diff] [blame]38 usb@c5008000 {
39 status = "okay";
Stephen Warren24bfee62012-05-21 10:04:37 +0000[diff] [blame]40 };
Marc Dietrichb81dfe12012-11-25 11:26:12 +0000[diff] [blame]41
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]42 sdhci@c8000000 {
43 status = "okay";
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]44 cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
45 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
46 power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]47 bus-width = <4>;
48 };
49
50 sdhci@c8000600 {
51 status = "okay";
52 bus-width = <8>;
53 };
54
Simon Glasse31a2a52016-01-30 16:37:52 -0700[diff] [blame]55 clocks {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <0>;
59
60 clk32k_in: clock@0 {
61 compatible = "fixed-clock";
62 reg=<0>;
63 #clock-cells = <0>;
64 clock-frequency = <32768>;
65 };
66 };
67
Marc Dietrichb81dfe12012-11-25 11:26:12 +0000[diff] [blame]68 lcd_panel: panel {
69 /* PAZ00 has 1024x600 */
70 clock = <54030000>;
71 xres = <1024>;
72 yres = <600>;
73 right-margin = <160>;
74 left-margin = <24>;
75 hsync-len = <136>;
76 upper-margin = <3>;
77 lower-margin = <61>;
78 vsync-len = <6>;
79 hsync-active-high;
80 nvidia,bits-per-pixel = <16>;
81 nvidia,pwm = <&pwm 0 0>;
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]82 nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(U, 4)
83 GPIO_ACTIVE_HIGH>;
84 nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(M, 6)
85 GPIO_ACTIVE_HIGH>;
86 nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
87 GPIO_ACTIVE_HIGH>;
88 nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(A, 4)
89 GPIO_ACTIVE_HIGH>;
Marc Dietrichb81dfe12012-11-25 11:26:12 +0000[diff] [blame]90 nvidia,panel-timings = <400 4 203 17 15>;
91 };
Stephen Warren24bfee62012-05-21 10:04:37 +0000[diff] [blame]92};