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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2002
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00006 */
7
8#ifndef _SPARTAN2_H_
9#define _SPARTAN2_H_
10
11#include <xilinx.h>
12
Wolfgang Denk74f9b382011-07-30 13:33:49 +000013extern int Spartan2_load(Xilinx_desc *desc, const void *image, size_t size);
14extern int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
15extern int Spartan2_info(Xilinx_desc *desc);
wdenkc6097192002-11-03 00:24:07 +000016
17/* Slave Parallel Implementation function table */
18typedef struct {
19 Xilinx_pre_fn pre;
20 Xilinx_pgm_fn pgm;
21 Xilinx_init_fn init;
22 Xilinx_err_fn err;
23 Xilinx_done_fn done;
24 Xilinx_clk_fn clk;
25 Xilinx_cs_fn cs;
26 Xilinx_wr_fn wr;
27 Xilinx_rdata_fn rdata;
28 Xilinx_wdata_fn wdata;
29 Xilinx_busy_fn busy;
30 Xilinx_abort_fn abort;
31 Xilinx_post_fn post;
wdenkc6097192002-11-03 00:24:07 +000032} Xilinx_Spartan2_Slave_Parallel_fns;
33
34/* Slave Serial Implementation function table */
35typedef struct {
wdenk1272e232002-11-10 22:06:23 +000036 Xilinx_pre_fn pre;
wdenkc6097192002-11-03 00:24:07 +000037 Xilinx_pgm_fn pgm;
38 Xilinx_clk_fn clk;
wdenk1272e232002-11-10 22:06:23 +000039 Xilinx_init_fn init;
40 Xilinx_done_fn done;
41 Xilinx_wr_fn wr;
Matthias Fuchs518e2e142007-12-27 17:12:43 +010042 Xilinx_post_fn post;
wdenkc6097192002-11-03 00:24:07 +000043} Xilinx_Spartan2_Slave_Serial_fns;
44
45/* Device Image Sizes
46 *********************************************************************/
47/* Spartan-II (2.5V) */
Wolfgang Denka1be4762008-05-20 16:00:29 +020048#define XILINX_XC2S15_SIZE 197728/8
49#define XILINX_XC2S30_SIZE 336800/8
50#define XILINX_XC2S50_SIZE 559232/8
51#define XILINX_XC2S100_SIZE 781248/8
52#define XILINX_XC2S150_SIZE 1040128/8
53#define XILINX_XC2S200_SIZE 1335872/8
wdenkc6097192002-11-03 00:24:07 +000054
wdenk02ac0212005-01-09 17:19:34 +000055/* Spartan-IIE (1.8V) */
56#define XILINX_XC2S50E_SIZE 630048/8
57#define XILINX_XC2S100E_SIZE 863840/8
58#define XILINX_XC2S150E_SIZE 1134496/8
59#define XILINX_XC2S200E_SIZE 1442016/8
60#define XILINX_XC2S300E_SIZE 1875648/8
61
wdenkc6097192002-11-03 00:24:07 +000062/* Descriptor Macros
63 *********************************************************************/
64/* Spartan-II devices */
65#define XILINX_XC2S15_DESC(iface, fn_table, cookie) \
66{ Xilinx_Spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie }
67
68#define XILINX_XC2S30_DESC(iface, fn_table, cookie) \
69{ Xilinx_Spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie }
70
71#define XILINX_XC2S50_DESC(iface, fn_table, cookie) \
72{ Xilinx_Spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie }
73
74#define XILINX_XC2S100_DESC(iface, fn_table, cookie) \
75{ Xilinx_Spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie }
76
77#define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
78{ Xilinx_Spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie }
79
Matthias Fuchs41481632007-12-27 17:12:56 +010080#define XILINX_XC2S200_DESC(iface, fn_table, cookie) \
81{ Xilinx_Spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie }
82
wdenk02ac0212005-01-09 17:19:34 +000083#define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
84{ Xilinx_Spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie }
85
86#define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \
87{ Xilinx_Spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie }
88
89#define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \
90{ Xilinx_Spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie }
91
92#define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \
93{ Xilinx_Spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie }
94
95#define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \
96{ Xilinx_Spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie }
97
wdenkc6097192002-11-03 00:24:07 +000098#endif /* _SPARTAN2_H_ */