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git01.mediatek.com / filogic / uboot / b1954254997f8616624b1f0b7bcd90c84ae0fabd / . / arch / powerpc / cpu / mpc85xx / t1040_serdes.c
blob: 94814ac13e6f4a124d7ebba999c61c1d366e2171 [file] [log] [blame]
York Sun46571362013-03-25 07:40:06 +0000[diff] [blame]1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
York Sun46571362013-03-25 07:40:06 +0000[diff] [blame]5 */
6
7#include <common.h>
8#include <asm/fsl_serdes.h>
9#include <asm/processor.h>
10#include <asm/io.h>
11#include "fsl_corenet2_serdes.h"
12
13static u8 serdes_cfg_tbl[MAX_SERDES][0xC4][SRDS_MAX_LANES] = {
14 { /* SerDes 1 */
15 [0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
16 PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1},
17 [0x66] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
18 PCIE2, PCIE3, PCIE4, SATA1},
19 [0x67] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
20 PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
21 [0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
22 PCIE2, PCIE2, PCIE2, PCIE2},
23 [0x8D] = {PCIE1, SGMII_SW1_DTSEC3, SGMII_SW1_DTSEC1, SGMII_SW1_DTSEC2,
24 PCIE2, SGMII_SW1_DTSEC6, SGMII_SW1_DTSEC4, SGMII_SW1_DTSEC5},
25 [0x89] = {PCIE1, SGMII_SW1_DTSEC3, SGMII_SW1_DTSEC1, SGMII_SW1_DTSEC2,
26 PCIE2, PCIE3, SGMII_SW1_DTSEC4, SATA1},
27 [0x86] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
28 PCIE2, PCIE3, PCIE4, SATA1},
29 [0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
30 PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
31 [0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
32 PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
33 [0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
34 PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
35 [0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
36 PCIE2, PCIE2, PCIE2, PCIE2},
37 [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1,
38 PCIE2, PCIE3, PCIE4, SATA1},
39 [0x08] = {PCIE1, PCIE1, PCIE1, PCIE1,
40 PCIE2, PCIE3, SATA2, SATA1},
41 [0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
42 AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
43 [0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
44 PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
45 [0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
46 PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
47 [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1,
48 PCIE2, PCIE2, PCIE2, PCIE2},
49 },
50 {
51 },
52 {
53 },
54 {
55 },
56};
57
58
59enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
60{
61 return serdes_cfg_tbl[serdes][cfg][lane];
62}
63
64int is_serdes_prtcl_valid(int serdes, u32 prtcl)
65{
66 int i;
67
Axel Linab95b092013-05-26 15:00:30 +0800[diff] [blame]68 if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl[serdes]))
York Sun46571362013-03-25 07:40:06 +0000[diff] [blame]69 return 0;
70
71 for (i = 0; i < SRDS_MAX_LANES; i++) {
72 if (serdes_cfg_tbl[serdes][prtcl][i] != NONE)
73 return 1;
74 }
75
76 return 0;
77}