Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / b1954254997f8616624b1f0b7bcd90c84ae0fabd / . / arch / powerpc / cpu / mpc85xx / p5040_serdes.c
blob: 2655974a455099590d9013bed7472cf6fa48f7d5 [file] [log] [blame]
Timur Tabid5e13882012-10-05 11:09:19 +0000[diff] [blame]1/*
2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
Timur Tabid5e13882012-10-05 11:09:19 +0000[diff] [blame]5 */
6
7#include <common.h>
8#include <asm/fsl_serdes.h>
9#include <asm/processor.h>
10#include <asm/io.h>
11#include "fsl_corenet_serdes.h"
12
13/*
14 * Note: For P5040, the fourth SerDes bank (with two lanes) is on SerDes2, but
15 * U-boot only supports one SerDes controller. Therefore, we ignore bank 4 in
16 * this table. This works because most of the SerDes code is for errata
17 * work-arounds, and there are no P5040 errata that effect bank 4.
18 */
19
20static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
21 [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
22 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
23 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
24 XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2, */ },
25 [0x01] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
26 SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1,
27 XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2,
28 XAUI_FM2, /* SATA1, SATA2 */ },
29 [0x02] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
30 SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
31 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2,
32 XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
33 [0x03] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC1,
34 SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
35 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
36 SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
37 /* SATA1, SATA2 */ },
38 [0x04] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM2_DTSEC1,
39 SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
40 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
41 SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
42 /* SATA1, SATA2 */ },
43 [0x05] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM1_DTSEC3,
44 SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
45 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2,
46 XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
47 [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
48 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
49 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
50 XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
51 [0x07] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
52 SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1,
53 XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2,
54 XAUI_FM2, /* SATA1, SATA2 */ },
55 [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
56 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
57 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2,
58 /* NONE, NONE */ },
59 [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
60 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
61 NONE, NONE, SATA1, SATA2, /* NONE, NONE */ },
62 [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
63 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
64 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2,
65 XAUI_FM2, XAUI_FM2, /* NONE, NONE */ },
66 [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1,
67 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
68 AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
69 NONE, SATA1, SATA2, /* NONE, NONE */ },
70 [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2,
71 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
72 XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2,
73 /* NONE, NONE */ },
74 [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
75 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
76 AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
77 NONE, SATA1, SATA2, /* NONE, NONE */ },
78};
79
80enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
81{
82 if (!serdes_lane_enabled(lane))
83 return NONE;
84
85 return serdes_cfg_tbl[cfg][lane];
86}
87
88int is_serdes_prtcl_valid(u32 prtcl)
89{
90 int i;
91
Axel Linab95b092013-05-26 15:00:30 +0800[diff] [blame]92 if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
Timur Tabid5e13882012-10-05 11:09:19 +0000[diff] [blame]93 return 0;
94
95 for (i = 0; i < SRDS_MAX_LANES; i++) {
96 if (serdes_cfg_tbl[prtcl][i] != NONE)
97 return 1;
98 }
99
100 return 0;
101}