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Kumar Gala5900ea72010-06-09 22:59:41 -05001/*
Jerry Huanged413672011-01-06 23:42:19 -06002 * Copyright 2010-2011 Freescale Semiconductor, Inc.
Kumar Gala5900ea72010-06-09 22:59:41 -05003 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala5900ea72010-06-09 22:59:41 -05005 */
6
7#include <common.h>
8#include <command.h>
9#include <linux/compiler.h>
10#include <asm/processor.h>
Timur Tabic5355dd2012-11-01 08:20:23 +000011#include "fsl_corenet_serdes.h"
Kumar Gala5900ea72010-06-09 22:59:41 -050012
Timur Tabie3ab8c12012-10-25 12:40:00 +000013#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
14/*
15 * This work-around is implemented in PBI, so just check to see if the
16 * work-around was actually applied. To do this, we check for specific data
17 * at specific addresses in DCSR.
18 *
19 * Array offsets[] contains a list of offsets within DCSR. According to the
20 * erratum document, the value at each offset should be 2.
21 */
22static void check_erratum_a4849(uint32_t svr)
23{
24 void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000;
25 unsigned int i;
26
27#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041)
28 static const uint8_t offsets[] = {
29 0x50, 0x54, 0x58, 0x90, 0x94, 0x98
30 };
31#endif
32#ifdef CONFIG_PPC_P4080
33 static const uint8_t offsets[] = {
34 0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac
35 };
36#endif
37 uint32_t x108; /* The value that should be at offset 0x108 */
38
39 for (i = 0; i < ARRAY_SIZE(offsets); i++) {
40 if (in_be32(dcsr + offsets[i]) != 2) {
41 printf("Work-around for Erratum A004849 is not enabled\n");
42 return;
43 }
44 }
45
46#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041)
47 x108 = 0x12;
48#endif
49
50#ifdef CONFIG_PPC_P4080
51 /*
52 * For P4080, the erratum document says that the value at offset 0x108
53 * should be 0x12 on rev2, or 0x1c on rev3.
54 */
55 if (SVR_MAJ(svr) == 2)
56 x108 = 0x12;
57 if (SVR_MAJ(svr) == 3)
58 x108 = 0x1c;
59#endif
60
61 if (in_be32(dcsr + 0x108) != x108) {
62 printf("Work-around for Erratum A004849 is not enabled\n");
63 return;
64 }
65
66 /* Everything matches, so the erratum work-around was applied */
67
68 printf("Work-around for Erratum A004849 enabled\n");
69}
70#endif
71
Timur Tabic5355dd2012-11-01 08:20:23 +000072#ifdef CONFIG_SYS_FSL_ERRATUM_A004580
73/*
74 * This work-around is implemented in PBI, so just check to see if the
75 * work-around was actually applied. To do this, we check for specific data
76 * at specific addresses in the SerDes register block.
77 *
78 * The work-around says that for each SerDes lane, write BnTTLCRy0 =
79 * 0x1B00_0001, Register 2 = 0x0088_0000, and Register 3 = 0x4000_0000.
80
81 */
82static void check_erratum_a4580(uint32_t svr)
83{
84 const serdes_corenet_t __iomem *srds_regs =
85 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
86 unsigned int lane;
87
88 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
89 if (serdes_lane_enabled(lane)) {
90 const struct serdes_lane __iomem *srds_lane =
91 &srds_regs->lane[serdes_get_lane_idx(lane)];
92
93 /*
94 * Verify that the values we were supposed to write in
95 * the PBI are actually there. Also, the lower 15
96 * bits of res4[3] should be the same as the upper 15
97 * bits of res4[1].
98 */
99 if ((in_be32(&srds_lane->ttlcr0) != 0x1b000001) ||
100 (in_be32(&srds_lane->res4[1]) != 0x880000) ||
101 (in_be32(&srds_lane->res4[3]) != 0x40000044)) {
102 printf("Work-around for Erratum A004580 is "
103 "not enabled\n");
104 return;
105 }
106 }
107 }
108
109 /* Everything matches, so the erratum work-around was applied */
110
111 printf("Work-around for Erratum A004580 enabled\n");
112}
113#endif
114
Kumar Gala5900ea72010-06-09 22:59:41 -0500115static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
116{
York Sun53155532012-08-08 18:04:53 +0000117#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
118 extern int enable_cpu_a011_workaround;
119#endif
Kumar Gala5900ea72010-06-09 22:59:41 -0500120 __maybe_unused u32 svr = get_svr();
121
122#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
123 if (IS_SVR_REV(svr, 1, 0)) {
124 switch (SVR_SOC_VER(svr)) {
125 case SVR_P1013:
Kumar Gala5900ea72010-06-09 22:59:41 -0500126 case SVR_P1022:
Kumar Gala5900ea72010-06-09 22:59:41 -0500127 puts("Work-around for Erratum SATA A001 enabled\n");
128 }
129 }
130#endif
131
Kumar Gala779a5322010-07-13 00:39:46 -0500132#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8)
133 puts("Work-around for Erratum SERDES8 enabled\n");
134#endif
Emil Medveb01c81f2010-08-31 22:57:38 -0500135#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9)
136 puts("Work-around for Erratum SERDES9 enabled\n");
137#endif
Timur Tabi90f381d2011-04-01 13:19:36 -0500138#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005)
139 puts("Work-around for Erratum SERDES-A005 enabled\n");
140#endif
Kumar Gala6b245b92010-05-05 22:35:27 -0500141#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
York Sund755c832012-05-07 07:26:45 +0000142 if (SVR_MAJ(svr) < 3)
143 puts("Work-around for Erratum CPU22 enabled\n");
Kumar Gala6b245b92010-05-05 22:35:27 -0500144#endif
York Sun9ed88112012-05-07 07:26:47 +0000145#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
146 /*
147 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
148 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
York Sun53155532012-08-08 18:04:53 +0000149 * The SVR has been checked by cpu_init_r().
York Sun9ed88112012-05-07 07:26:47 +0000150 */
York Sun53155532012-08-08 18:04:53 +0000151 if (enable_cpu_a011_workaround)
York Sun9ed88112012-05-07 07:26:47 +0000152 puts("Work-around for Erratum CPU-A011 enabled\n");
153#endif
Kumar Gala945e59a2011-11-22 06:51:15 -0600154#if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
155 puts("Work-around for Erratum CPU-A003999 enabled\n");
156#endif
York Sundf2be192011-11-20 10:01:35 -0800157#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474)
158 puts("Work-around for Erratum DDR-A003473 enabled\n");
159#endif
Becky Bruce4212f232010-12-17 17:17:58 -0600160#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
161 puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
162#endif
Jerry Huanged413672011-01-06 23:42:19 -0600163#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111)
164 puts("Work-around for Erratum ESDHC111 enabled\n");
165#endif
York Suna28496f2012-10-08 07:44:25 +0000166#ifdef CONFIG_SYS_FSL_ERRATUM_A004468
167 puts("Work-around for Erratum A004468 enabled\n");
168#endif
Roy Zang39356612011-01-07 00:06:47 -0600169#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135)
170 puts("Work-around for Erratum ESDHC135 enabled\n");
171#endif
Zang Roy-R6191183659922012-09-18 09:50:08 +0000172#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC13)
173 if (SVR_MAJ(svr) < 3)
174 puts("Work-around for Erratum ESDHC13 enabled\n");
Roy Zangc65dc4d2011-01-07 00:24:27 -0600175#endif
Kumar Gala9a878d52011-01-29 15:36:10 -0600176#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001)
177 puts("Work-around for Erratum ESDHC-A001 enabled\n");
178#endif
Kumar Gala9780b592011-01-13 01:54:01 -0600179#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
180 puts("Work-around for Erratum CPC-A002 enabled\n");
181#endif
Kumar Gala887c0e12011-01-13 01:56:18 -0600182#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
183 puts("Work-around for Erratum CPC-A003 enabled\n");
184#endif
Kumar Gala77b37af2011-01-13 02:58:23 -0600185#ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
186 puts("Work-around for Erratum ELBC-A001 enabled\n");
187#endif
York Sun922f40f2011-01-10 12:03:01 +0000188#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
189 puts("Work-around for Erratum DDR-A003 enabled\n");
190#endif
York Sun9aa857b2011-01-25 21:51:27 -0800191#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
192 puts("Work-around for Erratum DDR115 enabled\n");
193#endif
York Sunc8fc9592011-01-25 22:05:49 -0800194#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
195 puts("Work-around for Erratum DDR111 enabled\n");
196 puts("Work-around for Erratum DDR134 enabled\n");
197#endif
Poonam Aggrwalc7664a42011-06-30 03:00:28 -0500198#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
199 puts("Work-around for Erratum IFC-A002769 enabled\n");
200#endif
Poonam Aggrwalaf54a5f2011-06-29 16:32:52 +0530201#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
202 puts("Work-around for Erratum P1010-A003549 enabled\n");
203#endif
Poonam Aggrwal46b86ca2011-07-07 20:36:47 +0530204#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
205 puts("Work-around for Erratum IFC A-003399 enabled\n");
206#endif
Kumar Gala866c6fa2011-09-16 09:54:30 -0500207#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
208 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
209 puts("Work-around for Erratum NMG DDR120 enabled\n");
210#endif
Kumar Galaf3339d62011-10-03 08:37:57 -0500211#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
212 puts("Work-around for Erratum NMG_LBC103 enabled\n");
213#endif
chenhui zhaoc8caa8a2011-10-03 08:38:50 -0500214#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
215 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
216 puts("Work-around for Erratum NMG ETSEC129 enabled\n");
217#endif
Scott Wood80806962012-08-14 10:14:53 +0000218#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
219 puts("Work-around for Erratum A004510 enabled\n");
220#endif
Liu Gang712b6622012-09-28 21:26:19 +0000221#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
222 puts("Work-around for Erratum SRIO-A004034 enabled\n");
223#endif
York Sun6995a022012-10-08 07:44:26 +0000224#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
225 puts("Work-around for Erratum A004934 enabled\n");
226#endif
Shengzhou Liu95bd8e52013-01-23 19:56:23 +0000227#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
228 if (IS_SVR_REV(svr, 1, 0))
229 puts("Work-around for Erratum A005871 enabled\n");
230#endif
Timur Tabie3ab8c12012-10-25 12:40:00 +0000231#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
232 /* This work-around is implemented in PBI, so just check for it */
233 check_erratum_a4849(svr);
234#endif
Timur Tabic5355dd2012-11-01 08:20:23 +0000235#ifdef CONFIG_SYS_FSL_ERRATUM_A004580
236 /* This work-around is implemented in PBI, so just check for it */
237 check_erratum_a4580(svr);
238#endif
Yuanquan Chenc48234e2012-11-26 23:49:45 +0000239#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
240 puts("Work-around for Erratum PCIe-A003 enabled\n");
241#endif
Xuleicf4f4932013-03-11 17:56:34 +0000242#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
243 puts("Work-around for Erratum USB14 enabled\n");
244#endif
Scott Wood3f4a5c42013-05-15 17:50:13 -0500245#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
246 puts("Work-around for Erratum A006593 enabled\n");
247#endif
Shengzhou Liu097be702013-08-15 09:31:47 +0800248#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
249 if (IS_SVR_REV(svr, 1, 0))
250 puts("Work-around for Erratum A003571 enabled\n");
251#endif
York Suncca41c52013-06-25 11:37:49 -0700252#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
253 puts("Work-around for Erratum A-005812 enabled\n");
254#endif
York Sun0cc59072013-08-20 15:09:43 -0700255#ifdef CONFIG_SYS_FSL_ERRATUM_A005125
256 puts("Work-around for Erratum A005125 enabled\n");
257#endif
Chunhe Lan92546402013-08-16 15:10:37 +0800258#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
259 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
260 (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
261 puts("Work-around for Erratum I2C-A004447 enabled\n");
262#endif
Kumar Gala5900ea72010-06-09 22:59:41 -0500263 return 0;
264}
265
266U_BOOT_CMD(
267 errata, 1, 0, do_errata,
268 "Report errata workarounds",
269 ""
270);