| Jernej Skrabec | e331301 | 2021-01-11 21:11:37 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Sunxi H6 Power Management Unit register definition. |
| 4 | * |
| 5 | * (C) Copyright 2020 Jernej Skrabec <jernej.skrabec@siol.net> |
| 6 | */ |
| 7 | |
| 8 | #ifndef _SUN50I_PRCM_H |
| 9 | #define _SUN50I_PRCM_H |
| 10 | |
| 11 | #ifndef __ASSEMBLY__ |
| 12 | #include <linux/compiler.h> |
| 13 | |
| 14 | struct sunxi_prcm_reg { |
| 15 | u32 cpus_cfg; /* 0x000 */ |
| 16 | u8 res0[0x8]; /* 0x004 */ |
| 17 | u32 apbs1_cfg; /* 0x00c */ |
| 18 | u32 apbs2_cfg; /* 0x010 */ |
| 19 | u8 res1[0x108]; /* 0x014 */ |
| 20 | u32 tmr_gate_reset; /* 0x11c */ |
| 21 | u8 res2[0xc]; /* 0x120 */ |
| 22 | u32 twd_gate_reset; /* 0x12c */ |
| 23 | u8 res3[0xc]; /* 0x130 */ |
| 24 | u32 pwm_gate_reset; /* 0x13c */ |
| 25 | u8 res4[0x4c]; /* 0x140 */ |
| 26 | u32 uart_gate_reset; /* 0x18c */ |
| 27 | u8 res5[0xc]; /* 0x190 */ |
| 28 | u32 twi_gate_reset; /* 0x19c */ |
| 29 | u8 res6[0x1c]; /* 0x1a0 */ |
| 30 | u32 rsb_gate_reset; /* 0x1bc */ |
| 31 | u32 cir_cfg; /* 0x1c0 */ |
| 32 | u8 res7[0x8]; /* 0x1c4 */ |
| 33 | u32 cir_gate_reset; /* 0x1cc */ |
| 34 | u8 res8[0x10]; /* 0x1d0 */ |
| 35 | u32 w1_cfg; /* 0x1e0 */ |
| 36 | u8 res9[0x8]; /* 0x1e4 */ |
| 37 | u32 w1_gate_reset; /* 0x1ec */ |
| 38 | u8 res10[0x1c]; /* 0x1f0 */ |
| 39 | u32 rtc_gate_reset; /* 0x20c */ |
| 40 | }; |
| 41 | check_member(sunxi_prcm_reg, rtc_gate_reset, 0x20c); |
| 42 | |
| 43 | #define PRCM_TWI_GATE (1 << 0) |
| 44 | #define PRCM_TWI_RESET (1 << 16) |
| 45 | |
| 46 | #endif /* __ASSEMBLY__ */ |
| 47 | #endif /* _PRCM_H */ |