| Alexey Brodkin | b1566a5 | 2014-02-04 12:56:21 +0400 | [diff] [blame^] | 1 | Synopsys' DesignWare(r) ARC(r) Processors are a family of 32-bit CPUs |
| 2 | that SoC designers can optimize for a wide range of uses, from deeply embedded |
| 3 | to high-performance host applications. |
| 4 | |
| 5 | More information on ARC cores avaialble here: |
| 6 | http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx |
| 7 | |
| 8 | Designers can differentiate their products by using patented configuration |
| 9 | technology to tailor each ARC processor instance to meet specific performance, |
| 10 | power and area requirements. |
| 11 | |
| 12 | The DesignWare ARC processors are also extendable, allowing designers to add |
| 13 | their own custom instructions that dramatically increase performance. |
| 14 | |
| 15 | Synopsys' ARC processors have been used by over 170 customers worldwide who |
| 16 | collectively ship more than 1 billion ARC-based chips annually. |
| 17 | |
| 18 | All DesignWare ARC processors utilize a 16-/32-bit ISA that provides excellent |
| 19 | performance and code density for embedded and host SoC applications. |
| 20 | |
| 21 | The RISC microprocessors are synthesizable and can be implemented in any foundry |
| 22 | or process, and are supported by a complete suite of development tools. |
| 23 | |
| 24 | The ARC GNU toolchain with support for all ARC Processors can be downloaded |
| 25 | from here (available pre-built toolchains as well): |
| 26 | |
| 27 | https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases |