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Chin Liang See70fa4e72013-09-11 11:24:48 -05001/*
Ley Foon Tand5c5e3b2017-04-26 02:44:35 +08002 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
Chin Liang See70fa4e72013-09-11 11:24:48 -05003 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
Ley Foon Tand5c5e3b2017-04-26 02:44:35 +08007#ifndef _SYSTEM_MANAGER_H_
8#define _SYSTEM_MANAGER_H_
Chin Liang Seecca9f452013-12-30 18:26:14 -06009
Marek Vasut61412722014-09-08 14:08:45 +020010#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX (1 << 0)
11#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO (1 << 1)
12#define SYSMGR_ECC_OCRAM_EN (1 << 0)
13#define SYSMGR_ECC_OCRAM_SERR (1 << 3)
14#define SYSMGR_ECC_OCRAM_DERR (1 << 4)
15#define SYSMGR_FPGAINTF_USEFPGA 0x1
16#define SYSMGR_FPGAINTF_SPIM0 (1 << 0)
17#define SYSMGR_FPGAINTF_SPIM1 (1 << 1)
18#define SYSMGR_FPGAINTF_EMAC0 (1 << 2)
19#define SYSMGR_FPGAINTF_EMAC1 (1 << 3)
20#define SYSMGR_FPGAINTF_NAND (1 << 4)
21#define SYSMGR_FPGAINTF_SDMMC (1 << 5)
22
Dinh Nguyenc4b66c42015-12-02 13:31:33 -060023#define SYSMGR_SDMMC_DRVSEL_SHIFT 0
Marek Vasut61412722014-09-08 14:08:45 +020024
Pavel Machek57d75eb2014-09-08 14:08:45 +020025/* EMAC Group Bit definitions */
26#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
27#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
28#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
29
30#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
31#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
32#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3
33
Ley Foon Tand5c5e3b2017-04-26 02:44:35 +080034#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
35#include <asm/arch/system_manager_gen5.h>
36#endif
37
38#define SYSMGR_GET_BOOTINFO_BSEL(bsel) \
39 (((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7)
40
Chin Liang See70fa4e72013-09-11 11:24:48 -050041#endif /* _SYSTEM_MANAGER_H_ */