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Mike Frysinger4752c192008-10-12 21:32:52 -04001/*
2 * U-boot - main board file
3 *
4 * Copyright (c) 2008-2009 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <common.h>
10#include <config.h>
11#include <command.h>
12#include <net.h>
13#include <netdev.h>
14#include <spi.h>
15#include <asm/blackfin.h>
Mike Frysingerc5949182010-06-02 19:29:23 -040016#include <asm/portmux.h>
Mike Frysinger4752c192008-10-12 21:32:52 -040017#include <asm/mach-common/bits/otp.h>
Cliff Caie4638922009-11-20 08:24:43 +000018#include <asm/sdh.h>
Mike Frysinger4752c192008-10-12 21:32:52 -040019
20DECLARE_GLOBAL_DATA_PTR;
21
22int checkboard(void)
23{
24 printf("Board: ADI BF518F EZ-Board board\n");
25 printf(" Support: http://blackfin.uclinux.org/\n");
26 return 0;
27}
28
Mike Frysinger4752c192008-10-12 21:32:52 -040029#if defined(CONFIG_BFIN_MAC)
30static void board_init_enetaddr(uchar *mac_addr)
31{
Joe Hershberger522aba32015-05-04 14:55:15 -050032#ifndef CONFIG_SYS_NO_FLASH
33 /* we cram the MAC in the last flash sector */
34 uchar *board_mac_addr = (uchar *)0x203F0096;
35 if (is_valid_ethaddr(board_mac_addr)) {
36 memcpy(mac_addr, board_mac_addr, 6);
37 eth_setenv_enetaddr("ethaddr", mac_addr);
Mike Frysinger4752c192008-10-12 21:32:52 -040038 }
Joe Hershberger522aba32015-05-04 14:55:15 -050039#endif
Mike Frysinger4752c192008-10-12 21:32:52 -040040}
41
Mike Frysingerb361d6c2010-12-03 00:31:48 -050042/* Only the first run of boards had a KSZ switch */
43#if defined(CONFIG_BFIN_SPI) && __SILICON_REVISION__ == 0
44# define KSZ_POSSIBLE 1
45#else
46# define KSZ_POSSIBLE 0
47#endif
48
Graf Yanga211d4b2009-05-05 02:26:27 -040049#define KSZ_MAX_HZ 5000000
50
51#define KSZ_WRITE 0x02
52#define KSZ_READ 0x03
53
Mike Frysinger00136892009-05-29 18:00:16 -040054#define KSZ_REG_CHID 0x00 /* Register 0: Chip ID0 */
Graf Yanga211d4b2009-05-05 02:26:27 -040055#define KSZ_REG_STPID 0x01 /* Register 1: Chip ID1 / Start Switch */
56#define KSZ_REG_GC9 0x0b /* Register 11: Global Control 9 */
57#define KSZ_REG_P3C0 0x30 /* Register 48: Port 3 Control 0 */
58
59static int ksz8893m_transfer(struct spi_slave *slave, uchar dir, uchar reg,
Wolfgang Denkcc474d82009-05-15 22:32:57 +020060 uchar data, uchar result[3])
Graf Yanga211d4b2009-05-05 02:26:27 -040061{
62 unsigned char dout[3] = { dir, reg, data, };
63 return spi_xfer(slave, sizeof(dout) * 8, dout, result, SPI_XFER_BEGIN | SPI_XFER_END);
64}
65
66static int ksz8893m_reg_set(struct spi_slave *slave, uchar reg, uchar data)
67{
68 unsigned char din[3];
69 return ksz8893m_transfer(slave, KSZ_WRITE, reg, data, din);
70}
71
Mike Frysinger00136892009-05-29 18:00:16 -040072static int ksz8893m_reg_read(struct spi_slave *slave, uchar reg)
Graf Yanga211d4b2009-05-05 02:26:27 -040073{
Mike Frysinger00136892009-05-29 18:00:16 -040074 int ret;
Graf Yanga211d4b2009-05-05 02:26:27 -040075 unsigned char din[3];
Mike Frysinger00136892009-05-29 18:00:16 -040076 ret = ksz8893m_transfer(slave, KSZ_READ, reg, 0, din);
77 return ret ? ret : din[2];
78}
Graf Yanga211d4b2009-05-05 02:26:27 -040079
Mike Frysinger00136892009-05-29 18:00:16 -040080static int ksz8893m_reg_clear(struct spi_slave *slave, uchar reg, uchar mask)
81{
82 return ksz8893m_reg_set(slave, reg, ksz8893m_reg_read(slave, reg) & mask);
Graf Yanga211d4b2009-05-05 02:26:27 -040083}
84
85static int ksz8893m_reset(struct spi_slave *slave)
86{
87 int ret = 0;
88
89 /* Disable STPID mode */
90 ret |= ksz8893m_reg_clear(slave, KSZ_REG_GC9, 0x01);
91
92 /* Disable VLAN tag insert on Port3 */
93 ret |= ksz8893m_reg_clear(slave, KSZ_REG_P3C0, 0x04);
94
95 /* Start switch */
96 ret |= ksz8893m_reg_set(slave, KSZ_REG_STPID, 0x01);
97
98 return ret;
99}
100
Mike Frysingerb361d6c2010-12-03 00:31:48 -0500101static bool board_ksz_init(void)
Mike Frysinger4752c192008-10-12 21:32:52 -0400102{
Mike Frysingerb361d6c2010-12-03 00:31:48 -0500103 static bool switch_is_alive = false;
Mike Frysinger4752c192008-10-12 21:32:52 -0400104
105 if (!switch_is_alive) {
Graf Yanga211d4b2009-05-05 02:26:27 -0400106 struct spi_slave *slave = spi_setup_slave(0, 1, KSZ_MAX_HZ, SPI_MODE_3);
Mike Frysinger4752c192008-10-12 21:32:52 -0400107 if (slave) {
108 if (!spi_claim_bus(slave)) {
Mike Frysingerb361d6c2010-12-03 00:31:48 -0500109 bool phy_is_ksz = (ksz8893m_reg_read(slave, KSZ_REG_CHID) == 0x88);
110 int ret = phy_is_ksz ? ksz8893m_reset(slave) : 0;
Mike Frysinger00136892009-05-29 18:00:16 -0400111 switch_is_alive = (ret == 0);
Mike Frysinger4752c192008-10-12 21:32:52 -0400112 spi_release_bus(slave);
113 }
114 spi_free_slave(slave);
115 }
116 }
117
Mike Frysingerb361d6c2010-12-03 00:31:48 -0500118 return switch_is_alive;
119}
120
121int board_eth_init(bd_t *bis)
122{
123 if (KSZ_POSSIBLE) {
124 if (!board_ksz_init())
125 return 0;
126 }
127 return bfin_EMAC_initialize(bis);
Mike Frysinger4752c192008-10-12 21:32:52 -0400128}
129#endif
130
131int misc_init_r(void)
132{
133#ifdef CONFIG_BFIN_MAC
134 uchar enetaddr[6];
135 if (!eth_getenv_enetaddr("ethaddr", enetaddr))
136 board_init_enetaddr(enetaddr);
137#endif
138
Mike Frysinger04714b42011-03-17 17:14:14 -0400139#ifndef CONFIG_SYS_NO_FLASH
140 /* we use the last sector for the MAC address / POST LDR */
141 extern flash_info_t flash_info[];
142 flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, &flash_info[0]);
143#endif
144
Mike Frysinger4752c192008-10-12 21:32:52 -0400145 return 0;
146}
Graf Yang55e4b492009-05-24 02:34:34 -0400147
148int board_early_init_f(void)
149{
Mike Frysingerc5949182010-06-02 19:29:23 -0400150 /* connect async banks by default */
151 const unsigned short pins[] = {
152 P_AMS2, P_AMS3, 0,
153 };
154 return peripheral_request_list(pins, "async");
Graf Yang55e4b492009-05-24 02:34:34 -0400155}
Cliff Caie4638922009-11-20 08:24:43 +0000156
157#ifdef CONFIG_BFIN_SDH
158int board_mmc_init(bd_t *bis)
159{
160 return bfin_mmc_init(bis);
161}
162#endif