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Sughosh Ganu1b9c52b2010-11-30 11:25:01 -05001/*
2 * Modified for Hawkboard - Syed Mohammed Khasim <khasim@beagleboard.org>
3 *
4 * Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc. <nsekhar@ti.com>
5 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * Copyright (C) 2004 Texas Instruments.
7 *
8 * ----------------------------------------------------------------------------
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 * ----------------------------------------------------------------------------
23 */
24
25#include <common.h>
26#include <asm/errno.h>
27#include <asm/arch/hardware.h>
28#include <asm/io.h>
29#include <asm/arch/davinci_misc.h>
30#include <ns16550.h>
Wolfgang Denk0ae439f2011-09-10 22:26:28 +020031#include <nand.h>
Sughosh Ganu1b9c52b2010-11-30 11:25:01 -050032
33DECLARE_GLOBAL_DATA_PTR;
34
Sughosh Ganu1b9c52b2010-11-30 11:25:01 -050035static const struct pinmux_config mii_pins[] = {
36 { pinmux(2), 8, 1 },
37 { pinmux(2), 8, 2 },
38 { pinmux(2), 8, 3 },
39 { pinmux(2), 8, 4 },
40 { pinmux(2), 8, 5 },
41 { pinmux(2), 8, 6 },
42 { pinmux(2), 8, 7 }
43};
44
45static const struct pinmux_config mdio_pins[] = {
46 { pinmux(4), 8, 0 },
47 { pinmux(4), 8, 1 }
48};
49
50static const struct pinmux_config nand_pins[] = {
51 { pinmux(7), 1, 1 },
52 { pinmux(7), 1, 2 },
53 { pinmux(7), 1, 4 },
54 { pinmux(7), 1, 5 },
55 { pinmux(9), 1, 0 },
56 { pinmux(9), 1, 1 },
57 { pinmux(9), 1, 2 },
58 { pinmux(9), 1, 3 },
59 { pinmux(9), 1, 4 },
60 { pinmux(9), 1, 5 },
61 { pinmux(9), 1, 6 },
62 { pinmux(9), 1, 7 },
63 { pinmux(12), 1, 5 },
64 { pinmux(12), 1, 6 }
65};
66
67static const struct pinmux_config uart2_pins[] = {
68 { pinmux(0), 4, 6 },
69 { pinmux(0), 4, 7 },
70 { pinmux(4), 2, 4 },
71 { pinmux(4), 2, 5 }
72};
73
Sughosh Ganu1b9c52b2010-11-30 11:25:01 -050074static const struct pinmux_resource pinmuxes[] = {
75 PINMUX_ITEM(mii_pins),
76 PINMUX_ITEM(mdio_pins),
Sughosh Ganu1b9c52b2010-11-30 11:25:01 -050077 PINMUX_ITEM(nand_pins),
78 PINMUX_ITEM(uart2_pins),
79};
80
81static const struct lpsc_resource lpsc[] = {
82 { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
83 { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
84 { DAVINCI_LPSC_EMAC }, /* image download */
85 { DAVINCI_LPSC_UART2 }, /* console */
86 { DAVINCI_LPSC_GPIO },
87};
88
89void board_init_f(ulong bootflag)
90{
91 /*
92 * Kick Registers need to be set to allow access to Pin Mux registers
93 */
Christian Rieschaf5829ce2011-11-19 00:45:44 +000094 writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
95 writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
Sughosh Ganu1b9c52b2010-11-30 11:25:01 -050096
97 /* setup the SUSPSRC for ARM to control emulation suspend */
98 writel(readl(&davinci_syscfg_regs->suspsrc) &
99 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
100 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
101 DAVINCI_SYSCFG_SUSPSRC_UART2), &davinci_syscfg_regs->suspsrc);
102
103 /* Power on required peripherals
104 * ARM does not have acess by default to PSC0 and PSC1
105 * assuming here that the DSP bootloader has set the IOPU
106 * such that PSC access is available to ARM
107 */
108 da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc));
109
110 /* configure pinmux settings */
111 davinci_configure_pin_mux_items(pinmuxes,
112 ARRAY_SIZE(pinmuxes));
113
114 writel(readl(&davinci_uart2_ctrl_regs->pwremu_mgmt) |
115 (DAVINCI_UART_PWREMU_MGMT_FREE) |
116 (DAVINCI_UART_PWREMU_MGMT_URRST) |
117 (DAVINCI_UART_PWREMU_MGMT_UTRST),
118 &davinci_uart2_ctrl_regs->pwremu_mgmt);
119
120 NS16550_init((NS16550_t)(DAVINCI_UART2_BASE),
121 CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
122
123 puts("Nand boot...\n");
124
125 nand_boot();
126}
127
128void puts(const char *str)
129{
130 while (*str)
131 putc(*str++);
132}
133
134void putc(char c)
135{
136 if (gd->flags & GD_FLG_SILENT)
137 return;
138
139 if (c == '\n')
140 NS16550_putc((NS16550_t)(DAVINCI_UART2_BASE), '\r');
141
142 NS16550_putc((NS16550_t)(DAVINCI_UART2_BASE), c);
143}
144
145void hang(void)
146{
147 puts("### ERROR ### Please RESET the board ###\n");
148 for (;;)
149 ;
150}