| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| wdenk | e65527f | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 2 | /* |
| 3 | * MCF5282 Internal Memory Map |
| 4 | * |
| 5 | * Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de> |
| wdenk | e65527f | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __IMMAP_5282__ |
| 9 | #define __IMMAP_5282__ |
| 10 | |
| Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 11 | #define MMAP_SCM (CFG_SYS_MBAR + 0x00000000) |
| 12 | #define MMAP_SDRAMC (CFG_SYS_MBAR + 0x00000040) |
| 13 | #define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) |
| 14 | #define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100) |
| 15 | #define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000140) |
| 16 | #define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000180) |
| 17 | #define MMAP_DMA3 (CFG_SYS_MBAR + 0x000001C0) |
| 18 | #define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200) |
| 19 | #define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240) |
| 20 | #define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280) |
| 21 | #define MMAP_I2C (CFG_SYS_MBAR + 0x00000300) |
| 22 | #define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340) |
| 23 | #define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400) |
| 24 | #define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440) |
| 25 | #define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480) |
| 26 | #define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0) |
| 27 | #define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00) |
| 28 | #define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00) |
| 29 | #define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00) |
| 30 | #define MMAP_FEC (CFG_SYS_MBAR + 0x00001000) |
| 31 | #define MMAP_FECFIFO (CFG_SYS_MBAR + 0x00001400) |
| 32 | #define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000) |
| 33 | #define MMAP_CCM (CFG_SYS_MBAR + 0x00110000) |
| 34 | #define MMAP_PLL (CFG_SYS_MBAR + 0x00120000) |
| 35 | #define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000) |
| 36 | #define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000) |
| 37 | #define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000) |
| 38 | #define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000) |
| 39 | #define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000) |
| 40 | #define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000) |
| 41 | #define MMAP_QADC (CFG_SYS_MBAR + 0x00190000) |
| 42 | #define MMAP_GPTMRA (CFG_SYS_MBAR + 0x001A0000) |
| 43 | #define MMAP_GPTMRB (CFG_SYS_MBAR + 0x001B0000) |
| 44 | #define MMAP_CAN (CFG_SYS_MBAR + 0x001C0000) |
| 45 | #define MMAP_CFMC (CFG_SYS_MBAR + 0x001D0000) |
| 46 | #define MMAP_CFMMEM (CFG_SYS_MBAR + 0x04000000) |
| Heiko Schocher | ac1956e | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 47 | |
| Tom Rini | 3cb9c37 | 2023-10-12 19:03:56 -0400 | [diff] [blame] | 48 | #include <linux/types.h> |
| TsiChung Liew | 7f1a046 | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 49 | #include <asm/coldfire/eport.h> |
| 50 | #include <asm/coldfire/flexbus.h> |
| 51 | #include <asm/coldfire/flexcan.h> |
| 52 | #include <asm/coldfire/intctrl.h> |
| 53 | #include <asm/coldfire/qspi.h> |
| 54 | |
| TsiChungLiew | 0e81abc | 2007-08-15 19:38:15 -0500 | [diff] [blame] | 55 | /* System Control Module */ |
| 56 | typedef struct scm_ctrl { |
| 57 | u32 ipsbar; |
| 58 | u32 res1; |
| 59 | u32 rambar; |
| 60 | u32 res2; |
| 61 | u8 crsr; |
| 62 | u8 cwcr; |
| 63 | u8 lpicr; |
| 64 | u8 cwsr; |
| 65 | u32 res3; |
| 66 | u8 mpark; |
| 67 | u8 res4[3]; |
| 68 | u8 pacr0; |
| 69 | u8 pacr1; |
| 70 | u8 pacr2; |
| 71 | u8 pacr3; |
| 72 | u8 pacr4; |
| 73 | u8 res5; |
| 74 | u8 pacr5; |
| 75 | u8 pacr6; |
| 76 | u8 pacr7; |
| 77 | u8 res6; |
| 78 | u8 pacr8; |
| 79 | u8 res7; |
| 80 | u8 gpacr0; |
| 81 | u8 gpacr1; |
| 82 | u16 res8; |
| 83 | } scm_t; |
| Heiko Schocher | ac1956e | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 84 | |
| TsiChung Liew | 7f1a046 | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 85 | typedef struct canex_ctrl { |
| 86 | can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */ |
| 87 | } canex_t; |
| TsiChungLiew | 0e81abc | 2007-08-15 19:38:15 -0500 | [diff] [blame] | 88 | |
| 89 | /* Clock Module registers */ |
| 90 | typedef struct pll_ctrl { |
| 91 | u16 syncr; /* 0x00 synthesizer control register */ |
| 92 | u16 synsr; /* 0x02 synthesizer status register */ |
| 93 | } pll_t; |
| 94 | |
| 95 | /* Watchdog registers */ |
| 96 | typedef struct wdog_ctrl { |
| 97 | ushort wcr; |
| 98 | ushort wmr; |
| 99 | ushort wcntr; |
| 100 | ushort wsr; |
| 101 | } wdog_t; |
| wdenk | e65527f | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 102 | |
| TsiChungLiew | 0e81abc | 2007-08-15 19:38:15 -0500 | [diff] [blame] | 103 | #endif /* __IMMAP_5282__ */ |