Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / b0dfeac23b909bc0fb7f6e37076c4a76e19c928b / . / include / asm-arm / arch-omap3 / cpu.h
blob: c544e0c5d3a32e3a94f390267c5e5a1395935559 [file] [log] [blame]
Dirk Behmedeccb102008-12-14 09:47:11 +0100[diff] [blame]1/*
2 * (C) Copyright 2006-2008
3 * Texas Instruments, <www.ti.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24
25#ifndef _CPU_H
26#define _CPU_H
27
28/* Register offsets of common modules */
29/* Control */
30#ifndef __ASSEMBLY__
31typedef struct ctrl {
32 unsigned char res1[0xC0];
33 unsigned short gpmc_nadv_ale; /* 0xC0 */
34 unsigned short gpmc_noe; /* 0xC2 */
35 unsigned short gpmc_nwe; /* 0xC4 */
36 unsigned char res2[0x22A];
37 unsigned int status; /* 0x2F0 */
Dirk Behme2d0d4fa2009-02-12 18:55:42 +0100[diff] [blame]38 unsigned int gpstatus; /* 0x2F4 */
39 unsigned char res3[0x08];
40 unsigned int rpubkey_0; /* 0x300 */
41 unsigned int rpubkey_1; /* 0x304 */
42 unsigned int rpubkey_2; /* 0x308 */
43 unsigned int rpubkey_3; /* 0x30C */
44 unsigned int rpubkey_4; /* 0x310 */
45 unsigned char res4[0x04];
46 unsigned int randkey_0; /* 0x318 */
47 unsigned int randkey_1; /* 0x31C */
48 unsigned int randkey_2; /* 0x320 */
49 unsigned int randkey_3; /* 0x324 */
50 unsigned char res5[0x124];
51 unsigned int ctrl_omap_stat; /* 0x44C */
Dirk Behmedeccb102008-12-14 09:47:11 +0100[diff] [blame]52} ctrl_t;
53#else /* __ASSEMBLY__ */
54#define CONTROL_STATUS 0x2F0
55#endif /* __ASSEMBLY__ */
56
Dirk Behme2d0d4fa2009-02-12 18:55:42 +0100[diff] [blame]57/* cpu type */
58#define OMAP3503 0x5c00
59#define OMAP3515 0x1c00
60#define OMAP3525 0x4c00
61#define OMAP3530 0x0c00
62
Dirk Behme12dbcf62009-03-12 19:30:50 +0100[diff] [blame]63#ifndef __ASSEMBLY__
64typedef struct ctrl_id {
65 unsigned char res1[0x4];
66 unsigned int idcode; /* 0x04 */
67 unsigned int prod_id; /* 0x08 */
68 unsigned char res2[0x0C];
69 unsigned int die_id_0; /* 0x18 */
70 unsigned int die_id_1; /* 0x1C */
71 unsigned int die_id_2; /* 0x20 */
72 unsigned int die_id_3; /* 0x24 */
73} ctrl_id_t;
74#endif /* __ASSEMBLY__ */
75
Dirk Behmedeccb102008-12-14 09:47:11 +0100[diff] [blame]76/* device type */
77#define DEVICE_MASK (0x7 << 8)
78#define SYSBOOT_MASK 0x1F
79#define TST_DEVICE 0x0
80#define EMU_DEVICE 0x1
81#define HS_DEVICE 0x2
82#define GP_DEVICE 0x3
83
84/* GPMC CS3/cs4/cs6 not avaliable */
85#define GPMC_BASE (OMAP34XX_GPMC_BASE)
86#define GPMC_CONFIG_CS0 0x60
87#define GPMC_CONFIG_CS6 0x150
88#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
89#define GPMC_CONFIG_CS6_BASE (GPMC_BASE + GPMC_CONFIG_CS6)
90#define GPMC_CONFIG_WP 0x10
91
92#define GPMC_CONFIG_WIDTH 0x30
93
94#ifndef __ASSEMBLY__
95typedef struct gpmc {
96 unsigned char res1[0x10];
97 unsigned int sysconfig; /* 0x10 */
98 unsigned char res2[0x4];
99 unsigned int irqstatus; /* 0x18 */
100 unsigned int irqenable; /* 0x1C */
101 unsigned char res3[0x20];
102 unsigned int timeout_control; /* 0x40 */
103 unsigned char res4[0xC];
104 unsigned int config; /* 0x50 */
105 unsigned int status; /* 0x54 */
106 unsigned char res5[0x19C];
107 unsigned int ecc_config; /* 0x1F4 */
108 unsigned int ecc_control; /* 0x1F8 */
109 unsigned int ecc_size_config; /* 0x1FC */
110 unsigned int ecc1_result; /* 0x200 */
111 unsigned int ecc2_result; /* 0x204 */
112 unsigned int ecc3_result; /* 0x208 */
113 unsigned int ecc4_result; /* 0x20C */
114 unsigned int ecc5_result; /* 0x210 */
115 unsigned int ecc6_result; /* 0x214 */
116 unsigned int ecc7_result; /* 0x218 */
117 unsigned int ecc8_result; /* 0x21C */
118 unsigned int ecc9_result; /* 0x220 */
119} gpmc_t;
120
121typedef struct gpmc_csx {
122 unsigned int config1; /* 0x00 */
123 unsigned int config2; /* 0x04 */
124 unsigned int config3; /* 0x08 */
125 unsigned int config4; /* 0x0C */
126 unsigned int config5; /* 0x10 */
127 unsigned int config6; /* 0x14 */
128 unsigned int config7; /* 0x18 */
129 unsigned int nand_cmd; /* 0x1C */
130 unsigned int nand_adr; /* 0x20 */
131 unsigned int nand_dat; /* 0x24 */
132} gpmc_csx_t;
133#else /* __ASSEMBLY__ */
134#define GPMC_CONFIG1 0x00
135#define GPMC_CONFIG2 0x04
136#define GPMC_CONFIG3 0x08
137#define GPMC_CONFIG4 0x0C
138#define GPMC_CONFIG5 0x10
139#define GPMC_CONFIG6 0x14
140#define GPMC_CONFIG7 0x18
141#endif /* __ASSEMBLY__ */
142
143/* GPMC Mapping */
144#define FLASH_BASE 0x10000000 /* NOR flash, */
145 /* aligned to 256 Meg */
146#define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */
147 /* aligned to 64 Meg */
148#define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */
149 /* aligned to 256 Meg */
150#define DEBUG_BASE 0x08000000 /* debug board */
151#define NAND_BASE 0x30000000 /* NAND addr */
152 /* (actual size small port) */
153#define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */
154#define ONENAND_MAP 0x20000000 /* OneNand addr */
155 /* (actual size small port) */
156/* SMS */
157#ifndef __ASSEMBLY__
158typedef struct sms {
159 unsigned char res1[0x10];
160 unsigned int sysconfig; /* 0x10 */
161 unsigned char res2[0x34];
162 unsigned int rg_att0; /* 0x48 */
163 unsigned char res3[0x84];
164 unsigned int class_arb0; /* 0xD0 */
165} sms_t;
166#endif /* __ASSEMBLY__ */
167
168#define BURSTCOMPLETE_GROUP7 (0x1 << 31)
169
170/* SDRC */
171#ifndef __ASSEMBLY__
172typedef struct sdrc_cs {
173 unsigned int mcfg; /* 0x80 || 0xB0 */
174 unsigned int mr; /* 0x84 || 0xB4 */
175 unsigned char res1[0x4];
176 unsigned int emr2; /* 0x8C || 0xBC */
177 unsigned char res2[0x14];
178 unsigned int rfr_ctrl; /* 0x84 || 0xD4 */
179 unsigned int manual; /* 0xA8 || 0xD8 */
180 unsigned char res3[0x4];
181} sdrc_cs_t;
182
183typedef struct sdrc_actim {
184 unsigned int ctrla; /* 0x9C || 0xC4 */
185 unsigned int ctrlb; /* 0xA0 || 0xC8 */
186} sdrc_actim_t;
187
188typedef struct sdrc {
189 unsigned char res1[0x10];
190 unsigned int sysconfig; /* 0x10 */
191 unsigned int status; /* 0x14 */
192 unsigned char res2[0x28];
193 unsigned int cs_cfg; /* 0x40 */
194 unsigned int sharing; /* 0x44 */
195 unsigned char res3[0x18];
196 unsigned int dlla_ctrl; /* 0x60 */
197 unsigned int dlla_status; /* 0x64 */
198 unsigned int dllb_ctrl; /* 0x68 */
199 unsigned int dllb_status; /* 0x6C */
200 unsigned int power; /* 0x70 */
201 unsigned char res4[0xC];
202 sdrc_cs_t cs[2]; /* 0x80 || 0xB0 */
203} sdrc_t;
204#endif /* __ASSEMBLY__ */
205
206#define DLLPHASE_90 (0x1 << 1)
207#define LOADDLL (0x1 << 2)
208#define ENADLL (0x1 << 3)
209#define DLL_DELAY_MASK 0xFF00
210#define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8))
211
212#define PAGEPOLICY_HIGH (0x1 << 0)
213#define SRFRONRESET (0x1 << 7)
214#define WAKEUPPROC (0x1 << 26)
215
216#define DDR_SDRAM (0x1 << 0)
217#define DEEPPD (0x1 << 3)
218#define B32NOT16 (0x1 << 4)
219#define BANKALLOCATION (0x2 << 6)
220#define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */
221#define ADDRMUXLEGACY (0x1 << 19)
222#define CASWIDTH_10BITS (0x5 << 20)
223#define RASWIDTH_13BITS (0x2 << 24)
224#define BURSTLENGTH4 (0x2 << 0)
225#define CASL3 (0x3 << 4)
226#define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C)
227#define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4)
228#define ARE_ARCV_1 (0x1 << 0)
229#define ARCV (0x4e2 << 8) /* Autorefresh count */
230#define OMAP34XX_SDRC_CS0 0x80000000
231#define OMAP34XX_SDRC_CS1 0xA0000000
232#define CMD_NOP 0x0
233#define CMD_PRECHARGE 0x1
234#define CMD_AUTOREFRESH 0x2
235#define CMD_ENTR_PWRDOWN 0x3
236#define CMD_EXIT_PWRDOWN 0x4
237#define CMD_ENTR_SRFRSH 0x5
238#define CMD_CKE_HIGH 0x6
239#define CMD_CKE_LOW 0x7
240#define SOFTRESET (0x1 << 1)
241#define SMART_IDLE (0x2 << 3)
242#define REF_ON_IDLE (0x1 << 6)
243
244/* timer regs offsets (32 bit regs) */
245
246#ifndef __ASSEMBLY__
247typedef struct gptimer {
248 unsigned int tidr; /* 0x00 r */
249 unsigned char res[0xc];
250 unsigned int tiocp_cfg; /* 0x10 rw */
251 unsigned int tistat; /* 0x14 r */
252 unsigned int tisr; /* 0x18 rw */
253 unsigned int tier; /* 0x1c rw */
254 unsigned int twer; /* 0x20 rw */
255 unsigned int tclr; /* 0x24 rw */
256 unsigned int tcrr; /* 0x28 rw */
257 unsigned int tldr; /* 0x2c rw */
258 unsigned int ttgr; /* 0x30 rw */
259 unsigned int twpc; /* 0x34 r*/
260 unsigned int tmar; /* 0x38 rw*/
261 unsigned int tcar1; /* 0x3c r */
262 unsigned int tcicr; /* 0x40 rw */
263 unsigned int tcar2; /* 0x44 r */
264} gptimer_t;
265#endif /* __ASSEMBLY__ */
266
267/* enable sys_clk NO-prescale /1 */
268#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
269
270/* Watchdog */
271#ifndef __ASSEMBLY__
272typedef struct watchdog {
273 unsigned char res1[0x34];
274 unsigned int wwps; /* 0x34 r */
275 unsigned char res2[0x10];
276 unsigned int wspr; /* 0x48 rw */
277} watchdog_t;
278#endif /* __ASSEMBLY__ */
279
280#define WD_UNLOCK1 0xAAAA
281#define WD_UNLOCK2 0x5555
282
283/* PRCM */
284#define PRCM_BASE 0x48004000
285
286#ifndef __ASSEMBLY__
287typedef struct prcm {
288 unsigned int fclken_iva2; /* 0x00 */
289 unsigned int clken_pll_iva2; /* 0x04 */
290 unsigned char res1[0x1c];
291 unsigned int idlest_pll_iva2; /* 0x24 */
292 unsigned char res2[0x18];
293 unsigned int clksel1_pll_iva2 ; /* 0x40 */
294 unsigned int clksel2_pll_iva2; /* 0x44 */
295 unsigned char res3[0x8bc];
296 unsigned int clken_pll_mpu; /* 0x904 */
297 unsigned char res4[0x1c];
298 unsigned int idlest_pll_mpu; /* 0x924 */
299 unsigned char res5[0x18];
300 unsigned int clksel1_pll_mpu; /* 0x940 */
301 unsigned int clksel2_pll_mpu; /* 0x944 */
302 unsigned char res6[0xb8];
303 unsigned int fclken1_core; /* 0xa00 */
304 unsigned char res7[0xc];
305 unsigned int iclken1_core; /* 0xa10 */
306 unsigned int iclken2_core; /* 0xa14 */
307 unsigned char res8[0x28];
308 unsigned int clksel_core; /* 0xa40 */
309 unsigned char res9[0xbc];
310 unsigned int fclken_gfx; /* 0xb00 */
311 unsigned char res10[0xc];
312 unsigned int iclken_gfx; /* 0xb10 */
313 unsigned char res11[0x2c];
314 unsigned int clksel_gfx; /* 0xb40 */
315 unsigned char res12[0xbc];
316 unsigned int fclken_wkup; /* 0xc00 */
317 unsigned char res13[0xc];
318 unsigned int iclken_wkup; /* 0xc10 */
319 unsigned char res14[0xc];
320 unsigned int idlest_wkup; /* 0xc20 */
321 unsigned char res15[0x1c];
322 unsigned int clksel_wkup; /* 0xc40 */
323 unsigned char res16[0xbc];
324 unsigned int clken_pll; /* 0xd00 */
325 unsigned char res17[0x1c];
326 unsigned int idlest_ckgen; /* 0xd20 */
327 unsigned char res18[0x1c];
328 unsigned int clksel1_pll; /* 0xd40 */
329 unsigned int clksel2_pll; /* 0xd44 */
330 unsigned int clksel3_pll; /* 0xd48 */
331 unsigned char res19[0xb4];
332 unsigned int fclken_dss; /* 0xe00 */
333 unsigned char res20[0xc];
334 unsigned int iclken_dss; /* 0xe10 */
335 unsigned char res21[0x2c];
336 unsigned int clksel_dss; /* 0xe40 */
337 unsigned char res22[0xbc];
338 unsigned int fclken_cam; /* 0xf00 */
339 unsigned char res23[0xc];
340 unsigned int iclken_cam; /* 0xf10 */
341 unsigned char res24[0x2c];
342 unsigned int clksel_cam; /* 0xf40 */
343 unsigned char res25[0xbc];
344 unsigned int fclken_per; /* 0x1000 */
345 unsigned char res26[0xc];
346 unsigned int iclken_per; /* 0x1010 */
347 unsigned char res27[0x2c];
348 unsigned int clksel_per; /* 0x1040 */
349 unsigned char res28[0xfc];
350 unsigned int clksel1_emu; /* 0x1140 */
351} prcm_t;
352#else /* __ASSEMBLY__ */
353#define CM_CLKSEL_CORE 0x48004a40
354#define CM_CLKSEL_GFX 0x48004b40
355#define CM_CLKSEL_WKUP 0x48004c40
356#define CM_CLKEN_PLL 0x48004d00
357#define CM_CLKSEL1_PLL 0x48004d40
358#define CM_CLKSEL1_EMU 0x48005140
359#endif /* __ASSEMBLY__ */
360
361#define PRM_BASE 0x48306000
362
363#ifndef __ASSEMBLY__
364typedef struct prm {
365 unsigned char res1[0xd40];
366 unsigned int clksel; /* 0xd40 */
367 unsigned char res2[0x50c];
368 unsigned int rstctrl; /* 0x1250 */
369 unsigned char res3[0x1c];
370 unsigned int clksrc_ctrl; /* 0x1270 */
371} prm_t;
372#else /* __ASSEMBLY__ */
373#define PRM_RSTCTRL 0x48307250
374#endif /* __ASSEMBLY__ */
375
376#define SYSCLKDIV_1 (0x1 << 6)
377#define SYSCLKDIV_2 (0x1 << 7)
378
379#define CLKSEL_GPT1 (0x1 << 0)
380
381#define EN_GPT1 (0x1 << 0)
382#define EN_32KSYNC (0x1 << 2)
383
384#define ST_WDT2 (0x1 << 5)
385
386#define ST_MPU_CLK (0x1 << 0)
387
388#define ST_CORE_CLK (0x1 << 0)
389
390#define ST_PERIPH_CLK (0x1 << 1)
391
392#define ST_IVA2_CLK (0x1 << 0)
393
394#define RESETDONE (0x1 << 0)
395
396#define TCLR_ST (0x1 << 0)
397#define TCLR_AR (0x1 << 1)
398#define TCLR_PRE (0x1 << 5)
399
400/* SMX-APE */
401#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
402#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
403#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
404#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
405
406#ifndef __ASSEMBLY__
407typedef struct pm {
408 unsigned char res1[0x48];
409 unsigned int req_info_permission_0; /* 0x48 */
410 unsigned char res2[0x4];
411 unsigned int read_permission_0; /* 0x50 */
412 unsigned char res3[0x4];
413 unsigned int wirte_permission_0; /* 0x58 */
414 unsigned char res4[0x4];
415 unsigned int addr_match_1; /* 0x58 */
416 unsigned char res5[0x4];
417 unsigned int req_info_permission_1; /* 0x68 */
418 unsigned char res6[0x14];
419 unsigned int addr_match_2; /* 0x80 */
420} pm_t;
421#endif /*__ASSEMBLY__ */
422
423/* Permission values for registers -Full fledged permissions to all */
424#define UNLOCK_1 0xFFFFFFFF
425#define UNLOCK_2 0x00000000
426#define UNLOCK_3 0x0000FFFF
427
428#define NOT_EARLY 0
429
430/* I2C base */
431#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000)
432#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000)
433#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000)
434
435#endif /* _CPU_H */