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git01.mediatek.com / filogic / uboot / b097696d97f63e46e62552c1ca9f20778fd4fa65 / . / drivers / watchdog / stm32mp_wdt.c
blob: 8093d0a9f467b68ddb25cee1982126944449e5ae [file] [log] [blame]
Patrice Chotard473b2442019-04-30 17:26:22 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/*
3 * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
4 */
5
6#include <common.h>
7#include <clk.h>
8#include <dm.h>
9#include <syscon.h>
10#include <wdt.h>
11#include <asm/io.h>
12#include <linux/iopoll.h>
13
14/* IWDG registers */
15#define IWDG_KR 0x00 /* Key register */
16#define IWDG_PR 0x04 /* Prescaler Register */
17#define IWDG_RLR 0x08 /* ReLoad Register */
18#define IWDG_SR 0x0C /* Status Register */
19
20/* IWDG_KR register bit mask */
21#define KR_KEY_RELOAD 0xAAAA /* Reload counter enable */
22#define KR_KEY_ENABLE 0xCCCC /* Peripheral enable */
23#define KR_KEY_EWA 0x5555 /* Write access enable */
24
25/* IWDG_PR register bit values */
26#define PR_256 0x06 /* Prescaler set to 256 */
27
28/* IWDG_RLR register values */
29#define RLR_MAX 0xFFF /* Max value supported by reload register */
30
31/* IWDG_SR register bit values */
32#define SR_PVU BIT(0) /* Watchdog prescaler value update */
33#define SR_RVU BIT(1) /* Watchdog counter reload value update */
34
35struct stm32mp_wdt_priv {
36 fdt_addr_t base; /* registers addr in physical memory */
37 unsigned long wdt_clk_rate; /* Watchdog dedicated clock rate */
38};
39
40static int stm32mp_wdt_reset(struct udevice *dev)
41{
42 struct stm32mp_wdt_priv *priv = dev_get_priv(dev);
43
44 writel(KR_KEY_RELOAD, priv->base + IWDG_KR);
45
46 return 0;
47}
48
49static int stm32mp_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
50{
51 struct stm32mp_wdt_priv *priv = dev_get_priv(dev);
52 int reload;
53 u32 val;
54 int ret;
55
56 /* Prescaler fixed to 256 */
57 reload = timeout_ms * priv->wdt_clk_rate / 256;
58 if (reload > RLR_MAX + 1)
59 /* Force to max watchdog counter reload value */
60 reload = RLR_MAX + 1;
61 else if (!reload)
62 /* Force to min watchdog counter reload value */
63 reload = priv->wdt_clk_rate / 256;
64
65 /* Set prescaler & reload registers */
66 writel(KR_KEY_EWA, priv->base + IWDG_KR);
67 writel(PR_256, priv->base + IWDG_PR);
68 writel(reload - 1, priv->base + IWDG_RLR);
69
70 /* Enable watchdog */
71 writel(KR_KEY_ENABLE, priv->base + IWDG_KR);
72
73 /* Wait for the registers to be updated */
74 ret = readl_poll_timeout(priv->base + IWDG_SR, val,
75 val & (SR_PVU | SR_RVU), CONFIG_SYS_HZ);
76
77 if (ret < 0) {
78 pr_err("Updating IWDG registers timeout");
79 return -ETIMEDOUT;
80 }
81
82 return 0;
83}
84
85static int stm32mp_wdt_probe(struct udevice *dev)
86{
87 struct stm32mp_wdt_priv *priv = dev_get_priv(dev);
88 struct clk clk;
89 int ret;
90
91 debug("IWDG init\n");
92
93 priv->base = devfdt_get_addr(dev);
94 if (priv->base == FDT_ADDR_T_NONE)
95 return -EINVAL;
96
97 /* Enable clock */
98 ret = clk_get_by_name(dev, "pclk", &clk);
99 if (ret)
100 return ret;
101
102 ret = clk_enable(&clk);
103 if (ret)
104 return ret;
105
106 /* Get LSI clock */
107 ret = clk_get_by_name(dev, "lsi", &clk);
108 if (ret)
109 return ret;
110
111 priv->wdt_clk_rate = clk_get_rate(&clk);
112
113 debug("IWDG init done\n");
114
115 return 0;
116}
117
118static const struct wdt_ops stm32mp_wdt_ops = {
119 .start = stm32mp_wdt_start,
120 .reset = stm32mp_wdt_reset,
121};
122
123static const struct udevice_id stm32mp_wdt_match[] = {
124 { .compatible = "st,stm32mp1-iwdg" },
125 { /* sentinel */ }
126};
127
128U_BOOT_DRIVER(stm32mp_wdt) = {
129 .name = "stm32mp-wdt",
130 .id = UCLASS_WDT,
131 .of_match = stm32mp_wdt_match,
132 .priv_auto_alloc_size = sizeof(struct stm32mp_wdt_priv),
133 .probe = stm32mp_wdt_probe,
134 .ops = &stm32mp_wdt_ops,
135};