Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Jean-Christophe PLAGNIOL-VILLARD | 06a819c | 2009-06-13 20:50:02 +0200 | [diff] [blame] | 2 | /* |
| 3 | * include/asm-arm/macro.h |
| 4 | * |
| 5 | * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
Jean-Christophe PLAGNIOL-VILLARD | 06a819c | 2009-06-13 20:50:02 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __ASM_ARM_MACRO_H__ |
| 9 | #define __ASM_ARM_MACRO_H__ |
Alison Wang | 73818d5 | 2016-11-10 10:49:03 +0800 | [diff] [blame] | 10 | |
| 11 | #ifdef CONFIG_ARM64 |
| 12 | #include <asm/system.h> |
| 13 | #endif |
| 14 | |
Jean-Christophe PLAGNIOL-VILLARD | 06a819c | 2009-06-13 20:50:02 +0200 | [diff] [blame] | 15 | #ifdef __ASSEMBLY__ |
| 16 | |
| 17 | /* |
| 18 | * These macros provide a convenient way to write 8, 16 and 32 bit data |
| 19 | * to any address. |
| 20 | * Registers r4 and r5 are used, any data in these registers are |
| 21 | * overwritten by the macros. |
| 22 | * The macros are valid for any ARM architecture, they do not implement |
| 23 | * any memory barriers so caution is recommended when using these when the |
| 24 | * caches are enabled or on a multi-core system. |
| 25 | */ |
| 26 | |
| 27 | .macro write32, addr, data |
| 28 | ldr r4, =\addr |
| 29 | ldr r5, =\data |
| 30 | str r5, [r4] |
| 31 | .endm |
| 32 | |
| 33 | .macro write16, addr, data |
| 34 | ldr r4, =\addr |
| 35 | ldrh r5, =\data |
| 36 | strh r5, [r4] |
| 37 | .endm |
| 38 | |
| 39 | .macro write8, addr, data |
| 40 | ldr r4, =\addr |
| 41 | ldrb r5, =\data |
| 42 | strb r5, [r4] |
| 43 | .endm |
| 44 | |
| 45 | /* |
| 46 | * This macro generates a loop that can be used for delays in the code. |
| 47 | * Register r4 is used, any data in this register is overwritten by the |
| 48 | * macro. |
| 49 | * The macro is valid for any ARM architeture. The actual time spent in the |
| 50 | * loop will vary from CPU to CPU though. |
| 51 | */ |
| 52 | |
| 53 | .macro wait_timer, time |
| 54 | ldr r4, =\time |
| 55 | 1: |
| 56 | nop |
| 57 | subs r4, r4, #1 |
| 58 | bcs 1b |
| 59 | .endm |
| 60 | |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 61 | #ifdef CONFIG_ARM64 |
| 62 | /* |
| 63 | * Register aliases. |
| 64 | */ |
| 65 | lr .req x30 |
| 66 | |
| 67 | /* |
| 68 | * Branch according to exception level |
| 69 | */ |
| 70 | .macro switch_el, xreg, el3_label, el2_label, el1_label |
| 71 | mrs \xreg, CurrentEL |
| 72 | cmp \xreg, 0xc |
| 73 | b.eq \el3_label |
| 74 | cmp \xreg, 0x8 |
| 75 | b.eq \el2_label |
| 76 | cmp \xreg, 0x4 |
| 77 | b.eq \el1_label |
| 78 | .endm |
| 79 | |
| 80 | /* |
Bhupesh Sharma | 80a7e35 | 2015-01-23 15:50:04 +0530 | [diff] [blame] | 81 | * Branch if current processor is a Cortex-A57 core. |
| 82 | */ |
| 83 | .macro branch_if_a57_core, xreg, a57_label |
| 84 | mrs \xreg, midr_el1 |
| 85 | lsr \xreg, \xreg, #4 |
| 86 | and \xreg, \xreg, #0x00000FFF |
| 87 | cmp \xreg, #0xD07 /* Cortex-A57 MPCore processor. */ |
| 88 | b.eq \a57_label |
| 89 | .endm |
| 90 | |
| 91 | /* |
| 92 | * Branch if current processor is a Cortex-A53 core. |
| 93 | */ |
| 94 | .macro branch_if_a53_core, xreg, a53_label |
| 95 | mrs \xreg, midr_el1 |
| 96 | lsr \xreg, \xreg, #4 |
| 97 | and \xreg, \xreg, #0x00000FFF |
| 98 | cmp \xreg, #0xD03 /* Cortex-A53 MPCore processor. */ |
| 99 | b.eq \a53_label |
| 100 | .endm |
| 101 | |
| 102 | /* |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 103 | * Branch if current processor is a slave, |
| 104 | * choose processor with all zero affinity value as the master. |
| 105 | */ |
| 106 | .macro branch_if_slave, xreg, slave_label |
Linus Walleij | 7477139 | 2015-03-09 10:53:21 +0100 | [diff] [blame] | 107 | #ifdef CONFIG_ARMV8_MULTIENTRY |
| 108 | /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */ |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 109 | mrs \xreg, mpidr_el1 |
| 110 | tst \xreg, #0xff /* Test Affinity 0 */ |
| 111 | b.ne \slave_label |
| 112 | lsr \xreg, \xreg, #8 |
| 113 | tst \xreg, #0xff /* Test Affinity 1 */ |
| 114 | b.ne \slave_label |
| 115 | lsr \xreg, \xreg, #8 |
| 116 | tst \xreg, #0xff /* Test Affinity 2 */ |
| 117 | b.ne \slave_label |
| 118 | lsr \xreg, \xreg, #16 |
| 119 | tst \xreg, #0xff /* Test Affinity 3 */ |
| 120 | b.ne \slave_label |
Linus Walleij | 7477139 | 2015-03-09 10:53:21 +0100 | [diff] [blame] | 121 | #endif |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 122 | .endm |
| 123 | |
| 124 | /* |
| 125 | * Branch if current processor is a master, |
| 126 | * choose processor with all zero affinity value as the master. |
| 127 | */ |
| 128 | .macro branch_if_master, xreg1, xreg2, master_label |
Linus Walleij | 7477139 | 2015-03-09 10:53:21 +0100 | [diff] [blame] | 129 | #ifdef CONFIG_ARMV8_MULTIENTRY |
| 130 | /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */ |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 131 | mrs \xreg1, mpidr_el1 |
| 132 | lsr \xreg2, \xreg1, #32 |
zijun_hu | f489a4f | 2017-09-25 15:28:50 +0800 | [diff] [blame] | 133 | lsl \xreg2, \xreg2, #32 |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 134 | lsl \xreg1, \xreg1, #40 |
| 135 | lsr \xreg1, \xreg1, #40 |
| 136 | orr \xreg1, \xreg1, \xreg2 |
| 137 | cbz \xreg1, \master_label |
Linus Walleij | 7477139 | 2015-03-09 10:53:21 +0100 | [diff] [blame] | 138 | #else |
| 139 | b \master_label |
| 140 | #endif |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 141 | .endm |
| 142 | |
Alison Wang | 73818d5 | 2016-11-10 10:49:03 +0800 | [diff] [blame] | 143 | /* |
| 144 | * Switch from EL3 to EL2 for ARMv8 |
| 145 | * @ep: kernel entry point |
| 146 | * @flag: The execution state flag for lower exception |
| 147 | * level, ES_TO_AARCH64 or ES_TO_AARCH32 |
| 148 | * @tmp: temporary register |
| 149 | * |
| 150 | * For loading 32-bit OS, x1 is machine nr and x2 is ftaddr. |
| 151 | * For loading 64-bit OS, x0 is physical address to the FDT blob. |
| 152 | * They will be passed to the guest. |
| 153 | */ |
| 154 | .macro armv8_switch_to_el2_m, ep, flag, tmp |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 155 | msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */ |
Alison Wang | 73818d5 | 2016-11-10 10:49:03 +0800 | [diff] [blame] | 156 | mov \tmp, #CPTR_EL2_RES1 |
| 157 | msr cptr_el2, \tmp /* Disable coprocessor traps to EL2 */ |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 158 | |
David Feng | 9e2ea5a | 2015-03-02 15:29:34 +0800 | [diff] [blame] | 159 | /* Initialize Generic Timers */ |
| 160 | msr cntvoff_el2, xzr |
| 161 | |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 162 | /* Initialize SCTLR_EL2 |
| 163 | * |
| 164 | * setting RES1 bits (29,28,23,22,18,16,11,5,4) to 1 |
| 165 | * and RES0 bits (31,30,27,26,24,21,20,17,15-13,10-6) + |
| 166 | * EE,WXN,I,SA,C,A,M to 0 |
| 167 | */ |
Alison Wang | 73818d5 | 2016-11-10 10:49:03 +0800 | [diff] [blame] | 168 | ldr \tmp, =(SCTLR_EL2_RES1 | SCTLR_EL2_EE_LE |\ |
| 169 | SCTLR_EL2_WXN_DIS | SCTLR_EL2_ICACHE_DIS |\ |
| 170 | SCTLR_EL2_SA_DIS | SCTLR_EL2_DCACHE_DIS |\ |
| 171 | SCTLR_EL2_ALIGN_DIS | SCTLR_EL2_MMU_DIS) |
| 172 | msr sctlr_el2, \tmp |
| 173 | |
| 174 | mov \tmp, sp |
| 175 | msr sp_el2, \tmp /* Migrate SP */ |
| 176 | mrs \tmp, vbar_el3 |
| 177 | msr vbar_el2, \tmp /* Migrate VBAR */ |
| 178 | |
| 179 | /* Check switch to AArch64 EL2 or AArch32 Hypervisor mode */ |
| 180 | cmp \flag, #ES_TO_AARCH32 |
| 181 | b.eq 1f |
| 182 | |
| 183 | /* |
| 184 | * The next lower exception level is AArch64, 64bit EL2 | HCE | |
macro.wave.z@gmail.com | d8f5af9 | 2016-12-08 11:58:23 +0800 | [diff] [blame] | 185 | * RES1 (Bits[5:4]) | Non-secure EL0/EL1. |
| 186 | * and the SMD depends on requirements. |
Alison Wang | 73818d5 | 2016-11-10 10:49:03 +0800 | [diff] [blame] | 187 | */ |
macro.wave.z@gmail.com | d8f5af9 | 2016-12-08 11:58:23 +0800 | [diff] [blame] | 188 | #ifdef CONFIG_ARMV8_PSCI |
| 189 | ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\ |
| 190 | SCR_EL3_RES1 | SCR_EL3_NS_EN) |
| 191 | #else |
Alison Wang | 73818d5 | 2016-11-10 10:49:03 +0800 | [diff] [blame] | 192 | ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\ |
| 193 | SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\ |
| 194 | SCR_EL3_NS_EN) |
macro.wave.z@gmail.com | d8f5af9 | 2016-12-08 11:58:23 +0800 | [diff] [blame] | 195 | #endif |
Chee Hong Ang | b07ac0c | 2018-08-20 10:57:34 -0700 | [diff] [blame^] | 196 | |
| 197 | #ifdef CONFIG_ARMV8_EA_EL3_FIRST |
| 198 | orr \tmp, \tmp, #SCR_EL3_EA_EN |
| 199 | #endif |
Alison Wang | 73818d5 | 2016-11-10 10:49:03 +0800 | [diff] [blame] | 200 | msr scr_el3, \tmp |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 201 | |
| 202 | /* Return to the EL2_SP2 mode from EL3 */ |
Alison Wang | 73818d5 | 2016-11-10 10:49:03 +0800 | [diff] [blame] | 203 | ldr \tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\ |
| 204 | SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\ |
| 205 | SPSR_EL_M_AARCH64 | SPSR_EL_M_EL2H) |
| 206 | msr spsr_el3, \tmp |
| 207 | msr elr_el3, \ep |
| 208 | eret |
| 209 | |
| 210 | 1: |
| 211 | /* |
| 212 | * The next lower exception level is AArch32, 32bit EL2 | HCE | |
| 213 | * SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1. |
| 214 | */ |
| 215 | ldr \tmp, =(SCR_EL3_RW_AARCH32 | SCR_EL3_HCE_EN |\ |
| 216 | SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\ |
| 217 | SCR_EL3_NS_EN) |
| 218 | msr scr_el3, \tmp |
| 219 | |
| 220 | /* Return to AArch32 Hypervisor mode */ |
| 221 | ldr \tmp, =(SPSR_EL_END_LE | SPSR_EL_ASYN_MASK |\ |
| 222 | SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\ |
| 223 | SPSR_EL_T_A32 | SPSR_EL_M_AARCH32 |\ |
| 224 | SPSR_EL_M_HYP) |
| 225 | msr spsr_el3, \tmp |
| 226 | msr elr_el3, \ep |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 227 | eret |
| 228 | .endm |
| 229 | |
Alison Wang | 73818d5 | 2016-11-10 10:49:03 +0800 | [diff] [blame] | 230 | /* |
| 231 | * Switch from EL2 to EL1 for ARMv8 |
| 232 | * @ep: kernel entry point |
| 233 | * @flag: The execution state flag for lower exception |
| 234 | * level, ES_TO_AARCH64 or ES_TO_AARCH32 |
| 235 | * @tmp: temporary register |
| 236 | * |
| 237 | * For loading 32-bit OS, x1 is machine nr and x2 is ftaddr. |
| 238 | * For loading 64-bit OS, x0 is physical address to the FDT blob. |
| 239 | * They will be passed to the guest. |
| 240 | */ |
| 241 | .macro armv8_switch_to_el1_m, ep, flag, tmp |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 242 | /* Initialize Generic Timers */ |
Alison Wang | 73818d5 | 2016-11-10 10:49:03 +0800 | [diff] [blame] | 243 | mrs \tmp, cnthctl_el2 |
| 244 | /* Enable EL1 access to timers */ |
| 245 | orr \tmp, \tmp, #(CNTHCTL_EL2_EL1PCEN_EN |\ |
| 246 | CNTHCTL_EL2_EL1PCTEN_EN) |
| 247 | msr cnthctl_el2, \tmp |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 248 | msr cntvoff_el2, xzr |
| 249 | |
| 250 | /* Initilize MPID/MPIDR registers */ |
Alison Wang | 73818d5 | 2016-11-10 10:49:03 +0800 | [diff] [blame] | 251 | mrs \tmp, midr_el1 |
| 252 | msr vpidr_el2, \tmp |
| 253 | mrs \tmp, mpidr_el1 |
| 254 | msr vmpidr_el2, \tmp |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 255 | |
| 256 | /* Disable coprocessor traps */ |
Alison Wang | 73818d5 | 2016-11-10 10:49:03 +0800 | [diff] [blame] | 257 | mov \tmp, #CPTR_EL2_RES1 |
| 258 | msr cptr_el2, \tmp /* Disable coprocessor traps to EL2 */ |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 259 | msr hstr_el2, xzr /* Disable coprocessor traps to EL2 */ |
Alison Wang | 73818d5 | 2016-11-10 10:49:03 +0800 | [diff] [blame] | 260 | mov \tmp, #CPACR_EL1_FPEN_EN |
| 261 | msr cpacr_el1, \tmp /* Enable FP/SIMD at EL1 */ |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 262 | |
| 263 | /* SCTLR_EL1 initialization |
| 264 | * |
| 265 | * setting RES1 bits (29,28,23,22,20,11) to 1 |
| 266 | * and RES0 bits (31,30,27,21,17,13,10,6) + |
| 267 | * UCI,EE,EOE,WXN,nTWE,nTWI,UCT,DZE,I,UMA,SED,ITD, |
| 268 | * CP15BEN,SA0,SA,C,A,M to 0 |
| 269 | */ |
Alison Wang | 73818d5 | 2016-11-10 10:49:03 +0800 | [diff] [blame] | 270 | ldr \tmp, =(SCTLR_EL1_RES1 | SCTLR_EL1_UCI_DIS |\ |
| 271 | SCTLR_EL1_EE_LE | SCTLR_EL1_WXN_DIS |\ |
| 272 | SCTLR_EL1_NTWE_DIS | SCTLR_EL1_NTWI_DIS |\ |
| 273 | SCTLR_EL1_UCT_DIS | SCTLR_EL1_DZE_DIS |\ |
| 274 | SCTLR_EL1_ICACHE_DIS | SCTLR_EL1_UMA_DIS |\ |
| 275 | SCTLR_EL1_SED_EN | SCTLR_EL1_ITD_EN |\ |
| 276 | SCTLR_EL1_CP15BEN_DIS | SCTLR_EL1_SA0_DIS |\ |
| 277 | SCTLR_EL1_SA_DIS | SCTLR_EL1_DCACHE_DIS |\ |
| 278 | SCTLR_EL1_ALIGN_DIS | SCTLR_EL1_MMU_DIS) |
| 279 | msr sctlr_el1, \tmp |
| 280 | |
| 281 | mov \tmp, sp |
| 282 | msr sp_el1, \tmp /* Migrate SP */ |
| 283 | mrs \tmp, vbar_el2 |
| 284 | msr vbar_el1, \tmp /* Migrate VBAR */ |
| 285 | |
| 286 | /* Check switch to AArch64 EL1 or AArch32 Supervisor mode */ |
| 287 | cmp \flag, #ES_TO_AARCH32 |
| 288 | b.eq 1f |
| 289 | |
| 290 | /* Initialize HCR_EL2 */ |
| 291 | ldr \tmp, =(HCR_EL2_RW_AARCH64 | HCR_EL2_HCD_DIS) |
| 292 | msr hcr_el2, \tmp |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 293 | |
| 294 | /* Return to the EL1_SP1 mode from EL2 */ |
Alison Wang | 73818d5 | 2016-11-10 10:49:03 +0800 | [diff] [blame] | 295 | ldr \tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\ |
| 296 | SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\ |
| 297 | SPSR_EL_M_AARCH64 | SPSR_EL_M_EL1H) |
| 298 | msr spsr_el2, \tmp |
| 299 | msr elr_el2, \ep |
| 300 | eret |
| 301 | |
| 302 | 1: |
| 303 | /* Initialize HCR_EL2 */ |
| 304 | ldr \tmp, =(HCR_EL2_RW_AARCH32 | HCR_EL2_HCD_DIS) |
| 305 | msr hcr_el2, \tmp |
| 306 | |
| 307 | /* Return to AArch32 Supervisor mode from EL2 */ |
| 308 | ldr \tmp, =(SPSR_EL_END_LE | SPSR_EL_ASYN_MASK |\ |
| 309 | SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\ |
| 310 | SPSR_EL_T_A32 | SPSR_EL_M_AARCH32 |\ |
| 311 | SPSR_EL_M_SVC) |
| 312 | msr spsr_el2, \tmp |
| 313 | msr elr_el2, \ep |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 314 | eret |
| 315 | .endm |
| 316 | |
| 317 | #if defined(CONFIG_GICV3) |
| 318 | .macro gic_wait_for_interrupt_m xreg1 |
| 319 | 0 : wfi |
| 320 | mrs \xreg1, ICC_IAR1_EL1 |
| 321 | msr ICC_EOIR1_EL1, \xreg1 |
| 322 | cbnz \xreg1, 0b |
| 323 | .endm |
| 324 | #elif defined(CONFIG_GICV2) |
| 325 | .macro gic_wait_for_interrupt_m xreg1, wreg2 |
| 326 | 0 : wfi |
| 327 | ldr \wreg2, [\xreg1, GICC_AIAR] |
| 328 | str \wreg2, [\xreg1, GICC_AEOIR] |
Yehuda Yitschak | 07e2fd8 | 2014-10-27 14:07:16 +0200 | [diff] [blame] | 329 | and \wreg2, \wreg2, #0x3ff |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 330 | cbnz \wreg2, 0b |
| 331 | .endm |
| 332 | #endif |
| 333 | |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 334 | #endif /* CONFIG_ARM64 */ |
| 335 | |
Jean-Christophe PLAGNIOL-VILLARD | 06a819c | 2009-06-13 20:50:02 +0200 | [diff] [blame] | 336 | #endif /* __ASSEMBLY__ */ |
| 337 | #endif /* __ASM_ARM_MACRO_H__ */ |