blob: 0089ea64d6179a72064d90c764439a6f24c2452a [file] [log] [blame]
Marek Vasutb938f382017-07-21 23:16:59 +02001/*
2 * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board
3 *
4 * Copyright (C) 2016 Renesas Electronics Corp.
5 * Copyright (C) 2016 Cogent Embedded, Inc.
6 *
Marek Vasut07efb452017-11-29 04:27:36 +01007 * SPDX-License-Identifier: GPL-2.0
Marek Vasutb938f382017-07-21 23:16:59 +02008 */
9
10/dts-v1/;
11#include "r8a7795.dtsi"
Marek Vasut36f83d92017-09-12 23:01:51 +020012#include "ulcb.dtsi"
Marek Vasutb938f382017-07-21 23:16:59 +020013
14/ {
Marek Vasut36f83d92017-09-12 23:01:51 +020015 model = "Renesas H3ULCB board based on r8a7795 ES2.0+";
Marek Vasutb938f382017-07-21 23:16:59 +020016 compatible = "renesas,h3ulcb", "renesas,r8a7795";
17
Marek Vasutb938f382017-07-21 23:16:59 +020018 memory@48000000 {
19 device_type = "memory";
20 /* first 128MB is reserved for secure area. */
21 reg = <0x0 0x48000000 0x0 0x38000000>;
22 };
23
24 memory@500000000 {
25 device_type = "memory";
26 reg = <0x5 0x00000000 0x0 0x40000000>;
27 };
28
29 memory@600000000 {
30 device_type = "memory";
31 reg = <0x6 0x00000000 0x0 0x40000000>;
32 };
33
34 memory@700000000 {
35 device_type = "memory";
36 reg = <0x7 0x00000000 0x0 0x40000000>;
37 };
Marek Vasutb938f382017-07-21 23:16:59 +020038};
Marek Vasut07efb452017-11-29 04:27:36 +010039
40&du {
41 clocks = <&cpg CPG_MOD 724>,
42 <&cpg CPG_MOD 723>,
43 <&cpg CPG_MOD 722>,
44 <&cpg CPG_MOD 721>,
45 <&cpg CPG_MOD 727>,
46 <&versaclock5 1>,
47 <&versaclock5 3>,
48 <&versaclock5 4>,
49 <&versaclock5 2>;
50 clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
51 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
52};