| Lokesh Vutla | 56c8f0a | 2016-04-13 09:50:59 +0530 | [diff] [blame] | 1 | # |
| 2 | # Memory devices |
| 3 | # |
| 4 | |
| 5 | menu "Memory Controller drivers" |
| 6 | |
| Roger Quadros | b0679a7 | 2022-10-20 16:30:46 +0300 | [diff] [blame^] | 7 | config MEMORY |
| 8 | bool "Enable Driver Model for Memory Controller drivers" |
| 9 | depends on DM |
| 10 | help |
| 11 | Enable driver model for Memory Controller devices. |
| 12 | These devices provide Memory bus interface to various devices like |
| 13 | SRAM, Ethernet adapters, FPGAs, etc. |
| 14 | For now this uclass has no methods yet. |
| 15 | |
| 16 | config SANDBOX_MEMORY |
| 17 | bool "Enable Sandbox Memory Controller driver" |
| 18 | depends on SANDBOX && MEMORY |
| 19 | help |
| 20 | This is a driver model based Memory Controller driver for sandbox. |
| 21 | Currently it is a stub only, as there are no usable uclass methods |
| 22 | yet. |
| 23 | |
| Christophe Kerello | a994a80 | 2020-07-31 09:53:40 +0200 | [diff] [blame] | 24 | config STM32_FMC2_EBI |
| 25 | bool "Support for FMC2 External Bus Interface on STM32MP SoCs" |
| 26 | depends on ARCH_STM32MP |
| 27 | help |
| 28 | Select this option to enable the STM32 FMC2 External Bus Interface |
| 29 | controller. This driver configures the transactions with external |
| 30 | devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on |
| 31 | SOCs containing the FMC2 External Bus Interface. |
| 32 | |
| Lokesh Vutla | 56c8f0a | 2016-04-13 09:50:59 +0530 | [diff] [blame] | 33 | config TI_AEMIF |
| 34 | tristate "Texas Instruments AEMIF driver" |
| 35 | depends on ARCH_KEYSTONE |
| 36 | help |
| 37 | This driver is for the AEMIF module available in Texas Instruments |
| 38 | SoCs. AEMIF stands for Asynchronous External Memory Interface and |
| 39 | is intended to provide a glue-less interface to a variety of |
| 40 | asynchronuous memory devices like ASRAM, NOR and NAND memory. A total |
| 41 | of 256M bytes of any of these memories can be accessed at a given |
| 42 | time via four chip selects with 64M byte access per chip select. |
| 43 | |
| 44 | endmenu |