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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Joe Hershberger911c6062011-11-11 15:55:37 -06002
3#ifndef _MPC83XX_GPIO_H_
4#define _MPC83XX_GPIO_H_
5
6/*
7 * The MCP83xx's 1-2 GPIO controllers each with 32 bits.
8 */
Mario Six9164bdd2019-01-21 09:17:25 +01009#if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \
10 defined(CONFIG_ARCH_MPC8315)
Joe Hershberger911c6062011-11-11 15:55:37 -060011#define MPC83XX_GPIO_CTRLRS 1
Rasmus Villemoesb0673182019-12-12 09:18:52 +000012#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) || \
13 defined(CONFIG_ARCH_MPC8309)
Joe Hershberger911c6062011-11-11 15:55:37 -060014#define MPC83XX_GPIO_CTRLRS 2
15#else
16#define MPC83XX_GPIO_CTRLRS 0
17#endif
18
19#define MAX_NUM_GPIOS (32 * MPC83XX_GPIO_CTRLRS)
20
Mario Six5dec9e62019-01-21 09:18:08 +010021struct mpc8xxx_gpio_plat {
22 ulong addr;
23 unsigned long size;
24 uint ngpios;
25};
26
27#ifndef DM_GPIO
Joe Hershberger911c6062011-11-11 15:55:37 -060028void mpc83xx_gpio_init_f(void);
29void mpc83xx_gpio_init_r(void);
Mario Six5dec9e62019-01-21 09:18:08 +010030#endif /* DM_GPIO */
Joe Hershberger911c6062011-11-11 15:55:37 -060031
32#endif /* MPC83XX_GPIO_H_ */