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git01.mediatek.com / filogic / uboot / b04fc0f22f1a8aa015182f45a222176aeedad5a5 / . / board / ppmc8260 / ppmc8260.c
blob: 2b20c26f17478a43e56e108bf95df67b57865813 [file] [log] [blame]
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]1/*
2 * (C) Copyright 2000
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2001
7 * Advent Networks, Inc. <http://www.adventnetworks.com>
8 * Jay Monkman <jtm@smoothsmoothie.com>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <common.h>
30#include <ioports.h>
31#include <mpc8260.h>
32
33/*
34 * I/O Port configuration table
35 *
36 * if conf is 1, then that port pin will be configured at boot time
37 * according to the five values podr/pdir/ppar/psor/pdat for that entry
38 */
39
40const iop_conf_t iop_conf_tab[4][32] = {
41
42
43 /* Port A configuration */
44 { /* conf ppar psor pdir podr pdat */
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]45 /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 *ATMTXEN */
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]46 /* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTCA */
47 /* PA29 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTSOC */
48 /* PA28 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 *ATMRXEN */
49 /* PA27 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRSOC */
50 /* PA26 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRCA */
51 /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[0] */
52 /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[1] */
53 /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[2] */
54 /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[3] */
55 /* PA21 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[4] */
56 /* PA20 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[5] */
57 /* PA19 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[6] */
58 /* PA18 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[7] */
59 /* PA17 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
60 /* PA16 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
61 /* PA15 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
62 /* PA14 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
63 /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
64 /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
65 /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
66 /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
67 /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
68 /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
69 /* PA7 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_A1:L1TSYNC */
70 /* PA6 */ { 1, 0, 0, 1, 0, 0 }, /* TDN_A1:L1RSYNC */
71 /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
72 /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
73 /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
74 /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
75 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
76 /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
77 },
78
79 /* Port B configuration */
80 { /* conf ppar psor pdir podr pdat */
81 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
82 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
83 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
84 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
85 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
86 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
87 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
88 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
89 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
90 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
91 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
92 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
93 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
94 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
95 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
96 /* PB16 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_A1:L1CLK0 */
97 /* PB15 */ { 1, 0, 0, 1, 0, 1 }, /* /FETHRST */
98 /* PB14 */ { 1, 0, 0, 1, 0, 0 }, /* FETHDIS */
99 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
100 /* PB12 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_B1:L1CLK0 */
101 /* PB11 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1TXD */
102 /* PB10 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1RXD */
103 /* PB9 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1TSYNC */
104 /* PB8 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1RSYNC */
105 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
106 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
107 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
108 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
109 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
110 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
111 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
112 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
113 },
114
115 /* Port C */
116 { /* conf ppar psor pdir podr pdat */
117 /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
118 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
119 /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
120 /* PC28 */ { 1, 1, 0, 0, 0, 0 }, /* CLK4 */
121 /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
122 /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
123 /* PC25 */ { 1, 1, 0, 0, 0, 0 }, /* CLK7 */
124 /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
125 /* PC23 */ { 1, 0, 0, 1, 0, 0 }, /* ATMTFCLK */
126 /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
127 /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
128 /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
129 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
130 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
131 /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
132 /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
133 /* PC15 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:TxAddr[0] */
134 /* PC14 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[0] */
135 /* PC13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:TxAddr[1] */
136 /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[1] */
137 /* PC11 */ { 1, 1, 0, 1, 0, 0 }, /* TDM_D1:L1CLK0 */
138 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDC */
139 /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */
140 /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
141 /* PC7 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:TxAddr[2]*/
142 /* PC6 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[2] */
143 /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
144 /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
145 /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA2:DACK */
146 /* PC2 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA2:DONE */
147 /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA2:DREQ */
148 /* PC0 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA1:DREQ */
149 },
150
151 /* Port D */
152 { /* conf ppar psor pdir podr pdat */
153 /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */
154 /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */
155 /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[3] */
156 /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
157 /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
158 /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_C1:L1RSYNC */
159 /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
160 /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
161 /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
162 /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
163 /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
164 /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
165 /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
166 /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
167 /* PD17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
168 /* PD16 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
169 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
170 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
171 /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1TXD */
172 /* PD12 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1RXD */
173 /* PD11 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1TSYNC */
174 /* PD10 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1RSYNC*/
175 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1:TXD */
176 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1:RXD */
177 /* PD7 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1:SMSYN */
178 /* PD6 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA1:DACK */
179 /* PD5 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA1:DONE */
180 /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
181 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
182 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
183 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
184 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
185 }
186};
187
188/* ------------------------------------------------------------------------- */
189
190/*
191 * Check Board Identity:
192 */
193
194int checkboard (void)
195{
196 puts ("Board: Wind River PPMC8260\n");
197 return 0;
198}
199
200/* ------------------------------------------------------------------------- */
201
202long int initdram (int board_type)
203{
204 volatile immap_t *immap = (immap_t *) CFG_IMMR;
205 volatile memctl8260_t *memctl = &immap->im_memctl;
206 volatile uchar c = 0xff;
207 volatile uchar *ramaddr0 = (uchar *) (CFG_SDRAM0_BASE);
208 volatile uchar *ramaddr1 = (uchar *) (CFG_SDRAM1_BASE);
209 ulong psdmr = CFG_PSDMR;
210 volatile uchar *ramaddr2 = (uchar *) (CFG_SDRAM2_BASE);
211 ulong lsdmr = CFG_LSDMR;
212 int i;
213
214 /*
215 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
216 *
217 * "At system reset, initialization software must set up the
218 * programmable parameters in the memory controller banks registers
219 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
220 * system software should execute the following initialization sequence
221 * for each SDRAM device.
222 *
223 * 1. Issue a PRECHARGE-ALL-BANKS command
224 * 2. Issue eight CBR REFRESH commands
225 * 3. Issue a MODE-SET command to initialize the mode register
226 *
227 * The initial commands are executed by setting P/LSDMR[OP] and
228 * accessing the SDRAM with a single-byte transaction."
229 *
230 * The appropriate BRx/ORx registers have already been set when we
231 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
232 */
233
234 memctl->memc_psrt = CFG_PSRT;
235 memctl->memc_mptpr = CFG_MPTPR;
236
237#ifndef CFG_RAMBOOT
238 memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
239 *ramaddr0++ = c;
240 *ramaddr1++ = c;
241
242 memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
243 for (i = 0; i < 8; i++) {
244 *ramaddr0++ = c;
245 *ramaddr1++ = c;
246 }
247
248 memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
249 ramaddr0 = (uchar *) (CFG_SDRAM0_BASE + 0x110);
250 ramaddr1 = (uchar *) (CFG_SDRAM1_BASE + 0x110);
251 *ramaddr0 = c;
252 *ramaddr1 = c;
253
254 memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
255 *ramaddr0 = c;
256 *ramaddr1 = c;
257
258 memctl->memc_lsdmr = lsdmr | PSDMR_OP_PREA;
259 *ramaddr2++ = c;
260
261 memctl->memc_lsdmr = lsdmr | PSDMR_OP_CBRR;
262 for (i = 0; i < 8; i++) {
263 *ramaddr2++ = c;
264 }
265
266 memctl->memc_lsdmr = lsdmr | PSDMR_OP_MRW;
267 *ramaddr2++ = c;
268
269 memctl->memc_lsdmr = lsdmr | PSDMR_OP_NORM | PSDMR_RFEN;
270 *ramaddr2 = c;
271#endif
272
273 /* return total ram size */
274 return ((CFG_SDRAM0_SIZE + CFG_SDRAM1_SIZE) * 1024 * 1024);
275}
276
277#ifdef CONFIG_MISC_INIT_R
278/* ------------------------------------------------------------------------- */
279int misc_init_r (void)
280{
281#ifdef CFG_LED_BASE
282 uchar ds = *(unsigned char *) (CFG_LED_BASE + 1);
283 uchar ss;
284 uchar tmp[64];
285 int res;
286
287 if ((ds != 0) && (ds != 0xff)) {
Wolfgang Denk7fb52662005-10-13 16:45:02 +0200[diff] [blame]288 res = getenv_r ("ethaddr", (char *)tmp, sizeof (tmp));
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]289 if (res > 0) {
290 ss = ((ds >> 4) & 0x0f);
291 ss += ss < 0x0a ? '0' : ('a' - 10);
292 tmp[15] = ss;
293
294 ss = (ds & 0x0f);
295 ss += ss < 0x0a ? '0' : ('a' - 10);
296 tmp[16] = ss;
297
298 tmp[17] = '\0';
Wolfgang Denk7fb52662005-10-13 16:45:02 +0200[diff] [blame]299 setenv ("ethaddr", (char *)tmp);
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]300 /* set the led to show the address */
301 *((unsigned char *) (CFG_LED_BASE + 1)) = ds;
302 }
303 }
304#endif /* CFG_LED_BASE */
305 return (0);
306}
307#endif /* CONFIG_MISC_INIT_R */